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Co-designing CMOS circuits and quantum processors: new paper at DATE 2018

Designing a quantum computer is not an easy task. Recently, we developed a  methodology (and the relative tools) to co-design electronic circuits and quantum bits (qubits).

It will be presented at the DATE 2018 conference (Design, Automation and Test in Europe) in March in Dresden (Germany).

Check out our work if you want to simulate qubits in Cadence next to your CMOS circuit:

  • Jeroen van Dijk, Andrei Vladimirescu, Masoud Babaie, Edoardo Charbon, Fabio Sebastiano, “A Co-design Methodology for Scalable Quantum Processors and their Classical Electronic Interface”

2 papers at ISSCC 2018!

The following 2 papers have been accepted for presenation at the 2018 International Solid-State Circuits Conference (ISSCC) (a.k.a. the chip Olympics)!

  • Ç. Gürleyük, L. Pedalà, F. Sebastiano, K. A. A. Makinwa, “A CMOS Dual-RC Frequency Reference with ±250ppm Inaccuracy from -45°C to 85°C”
  • S. Karmakar, B. Gönen, F. Sebastiano, R. Van Veldhoven, K. A. A. Makinwa, “A 280μW Dynamic-Zoom ADC with 120dB DR and 118dB SNDR in 1kHz BW”

Check out the ISSCC 2018 technical program