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Spring talks on cryo-CMOS

April has come with a cold start of the Spring in The Netherlands, but also with plenty of talks and tutorials on cryo-CMOS. You can see me at:

Due to the on-line or hybrid nature of those events (which allowed me to participate in 2 conferences in US and one in Taiwan within a very short time), those talks have been recorded. So, if you miss them, please let me know and I can send you the video.

ISSCC 2020 Jan van Vessem Award for Oustanding European Paper

Very proud to receive the prestiguious Jan van Vessem Award for the work we presented at ISSCC 2020: ‘A Scalable Cryo-CMOS 2-to-20GHz Digitally Intensive Controller for 4×32 Frequency Multiplexed Spin Qubits/Transmons in 22nm FinFET Technology for Quantum Computers’.

More details about the work here: ‘Cryo-chip overcomes obstacle to large-scale quantum computers’.

Invited talk at IEEE Quantum Week

In the context of IEEE Quantum Week, I have been invited to give a talk at the Workshop on Semiconductor-Inspired Engineering for Quantum Computing. Join (virtually) on Oct.12th to hear about Cryo-CMOS for Silicon Qubits.

Special Session on Quantum Computing at ISCAS 2020

It has been delayed becuase of COVID, but ISCAS 2020 (International Symposium on Circuits and Systems) is finally happenning (virtually) from Oct. 10th to Oct.21st.

Please check out on Oct. 14th the Special Session on Quantum Computers that I co-organized with other colleagues (E.Blokhina, UCD; A. Vladimirescu, UC Berkeley, C. Almudever, TUD).

SPECIAL SESSION: The art of Building Large-scale Quantum Computers: From Physics to Engineering Session

With talks from UCD (Ireland), EPFL (Switzerland), Aarhus University (Denmark), and Johannes Kepler University Linz (Austria), the session will span several topics and several disciplines as requested to build a complex system as a quantum computer, ranging from quatum device fabrication and operation, thorugh (cryogenic) electrical control, to quantum compilation and quantum algorithms.

2 papers at ISSCC 2020!

We have 2 papers accepted at the next International Solid-State Circuit Conference, the major forum for the presentation of advances in integrated circuits!

We are showing advances in the filed of cryo-CMOS circuits for control of quantum processors. Check them in the advance ISSCC program.

A Scalable Cryo-CMOS 2-to-20GHz Digitally Intensive Controller for 4×32 Frequency Multiplexed Spin Qubits/Transmons in 22nm FinFET Technology for Quantum Computers

B. Patra*1, J. P. G. van Dijk*1, S. Subramanian2, A. Corna1, X. Xue1, C. Jeon2, F. Sheikh2, E. Juarez-Hernandez3, B. Perez Esparza3, H. Rampurawala2, B. Carlton2, N. Samkharadze4, S. Ravikumar2, C. Nieva2, S. Kim2, H-J. Lee2, A. Sammak4, G. Scappucci1, M. Veldhorst1, L. M. K. Vandersypen1,2, M. Babaie*1, F. Sebastiano*1, E. Charbon*2,5, S. Pellerano*2

*Equally-Credited Authors (ECAs)

1Delft University of Technology, Delft, The Netherlands
2Intel, Hillsboro, OR
3Intel, Guadalajara, Mexico
4TNO, Delft, The Netherlands
5EPFL, Neuchatel, Switzerland


A 200dB FoM 4-to-5GHz Cryogenic Oscillator with an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications

J. Gong1, Y. Chen1, F. Sebastiano1, E. Charbon2,3, M. Babaie1

1Delft University of Technology, Delft, The Netherlands
2EPFL, Lausanne, Switzerland
3Intel, Hillsboro, OR

Check the ISSCC 2020 advance program here.

Our paper on the impact of the electronics on a quantum computer is on-line in Phys. Rev. Appl.

After a long wait, our paper has been published in Physical Review Applied (see more information below). The paper describes how the performance of the interface electronics affects the performance of the whole quantum computer. The analysis is extremely relevant to derive the exact specification for the electronics so that we can design electronics good enough for the task but not overdesigned. This allows cutting unnecessary margins int eh electronics and enable to push further the optimization of the electronics. For example, we have used those techniques to design circuits that can consume much less power. This is extremely relevant when designing cryogenic circuits, for which the power consumption is strictly limited by the cooling power of existing refrigerators.

 The paper is available here:

Impact of Classical Control Electronics on Qubit Fidelity

J.P.G. van Dijk, E. Kawakami, R.N. Schouten, M. Veldhorst, L.M.K. Vandersypen, M. Babaie, E. Charbon, and F. Sebastiano

Phys. Rev. Applied 12, 044054 (2019) – Published 24 October 2019

Brief summary A quantum computer comprises both qubits and their classical electronic interface. While much research is currently devoted solely to qubits, an efficient electronic controller is also urgently needed for a scalable quantum computer. This study uses analytical techniques to expose the effect of nonideal circuit blocks in a classical controller on qubit fidelity, for all required operations, and how fidelity is affected by the limited performance of the general-purpose, room-temperature equipment typically used with the few qubits types available today. Tailor-made controllers can achieve significantly lower cost, power consumption, and size, as required for scaling up.

Abstract Quantum processors rely on classical electronic controllers to manipulate and read out the state of quantum bits (qubits). As the performance of the quantum processor improves, nonidealities in the classical controller can become the performance bottleneck for the whole quantum computer. To prevent such limitation, this paper presents a systematic study of the impact of the classical electrical signals on the qubit fidelity. All operations, i.e., single-qubit rotations, two-qubit gates, and readout, are considered, in the presence of errors in the control electronics, such as static, dynamic, systematic, and random errors. Although the presented study could be extended to any qubit technology, it currently focuses on single-electron spin qubits, because of several advantages, such as purely electrical control and long coherence times, and for their potential for large-scale integration. As a result of this study, detailed electrical specifications for the classical control electronics for a given qubit fidelity can be derived. We also discuss how qubit fidelity is affected by the limited performance of the general-purpose room-temperature equipment typically employed to control the few qubits available today. Ultimately, we show that tailor-made electronic controllers can achieve significantly lower power, cost, and size, as required to support the scaling up of quantum computers.



Webinar for SSCS on June 27th on Cryo-CMOS

Coming Thursday, June 27th, at 10:00 AM ET, I’ll give a webinar on  “Cryogenic CMOS Interfaces for Large-Scale Quantum Computers”. The webinar is organized by the IEEE Solid-State Circuit Society and you can register to attend here.

There will be the opportunity to ask questions. I hope many of you will join!


New “News and views” article in Nature electronics

My article in the “News and views” section of Nature Electronics has just been published on-line. You can find it freely available here:

In this piece, titled “Scalable read-out schemes for qubits“, I comment on the latest results by Dr. Fernando Gonzalez-Zalba at Hitachi Cambridge Laboratory on selective DRAM-like readout of spin qubits (also published in Nature Electronics). I give my views on current state-of-the-art on electronic interfaces for solid-state quantum processors and outline the path that electrical and Quantum Engineers will have to follow to give birth to scalable quantum computers.


Two Cryo-CMOS papers at ESSCIRC/ESSDERC 2019

The work of two of my Ph.D. students has been accepted for presentation at the coming ESSCIRC/ESSDERC conferences to be held in Krakow, Poland next September. Congratulations to Job and Pascal!

Job’s work is showing how to build a voltage reference in standard CMOS that can operate over the whole ultra-wide temperature range from 4 K to 300 K. And, for the first time, we are showing significant statistical data demonstrating the accuracy of such references down to cryogenic temperature.

In the other paper by Pascal, we focus on device characterization of CMOS transistors at cryogenic temperature. We extend our prior work on cryo-CMOS mismatch by showing the characterization of transistor mismatch over a wide range of operating regimes, from strong inversion down to weak inversion. In particular, weak inversion operation is very relevant as it allows for low-power operation,  as required in several power-limited cryogenic applications, such as quantum computing.

Both papers will be presented on the first day of the conference, on Tuesday morning and afternoon. See here.


  • Job van Staveren, Carmina Garcia Almudever, Giordano Scappucci, Menno Veldhorst, Masoud Babaie, Edoardo Charbon, Fabio Sebastiano, “Voltage References for the Ultra-Wide Temperature Range from 4.2K to 300K in 40-nm CMOS,” to be presented at ESSCIRC 2019.
  • Pascal A. ‘T Hart, Masoud Babaie, Edoardo Charbon, Andrei Vladimirescu, Fabio Sebastiano, “Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures,” to be presented at ESSDERC 2019.

Special Session on Quantum Computing at ISCAS 2019

This year, I organized a session on Quantum Computing at ISCAS 2019 in Japan!

The International Symposium on Circuits and Systems will be held in Sapporo, Japan, from May 26th to May 29th. The session titled “Towards Large-Scale Quantum Computers Session” will be held on May 28th at 14:50. More information here.

Six speakers from top-notch groups around the world will discuss the challenges and the research opportunities to be addressed on the path to build a quanutm computer with enough computing power to solve relevant problems, such as simulating a quantum systems like complex molecules and materials. The talks will span the whole stack of discipline required to build such a complex machine, ranging from quantum physics, thorugh electrical engineering and circuit design and up to computer architectures and quanutm compilers.

Join the session if you are in Sapporo!

A list of the papers below:

  1. Semiconductor spin qubits – a scalable platform for quantum computing? L. Schreiber, H. Bluhm, RWTH Aachen University, Germany
  1. Benefits and Challenges of Designing Cryogenic CMOS RF Circuits for Quantum Computer, M.Babaie1, M. Mehrpoo1, B. Patra1, J. Gong1, J.P.G. van Dijk1, P.A. ‘t Hart1, G. Kiene1, A. Vladimirescu1,2,3, F. Sebastiano1, E. Charbon1,4,5, 1Delft University of Technology, The Netherlands2University of California at Berkeley, U.S.,3Institut Supérieur d’Electronique de Paris, France 4EPFL, Switzerland5Intel, U.S.
  1. Systems Engineering of Cryogenic CMOS Electronics for Scalable Quantum Computers, C. Degenhardt1, A. Artanov1, V. Christ1, L. Geck1, C. Grewing1, A. Kruth1, D. Liebau1, P. Muralidharan1, D. Nielinger1, P. Schubert1, P. Vliex1, A. Zambanini1, and S. van Waasen1,2 1Forschungszentrum Jülich GmbH, Jülich, Germany2University of Duisburg-Essen, Germany
  1. Cryogenic support circuits and systems for silicon quantum computers, Torsten Lehmann, UNSW, Australia
  1. Quantum Accelerated Computer Architectures, L. Riesebos, X. Fu, A. A. Moueddenne, L. Lao, S. Varsamopoulos, I. Ashraf, J. van Someren, N. Khammassi, C. G. Almudever, K. Bertels, Delft University of Technology, The Netherlands
  1. Reducing the Overhead of Mapping Quantum Circuits to IBM Q Systems, Atsushi Matshuo, Wakaki Hattori and Shigeru Yamashita, Ritsumeikan University, Japan

The papers are already available on IEEExplore.