On this website, you will find my resume, a searchable list of my publications and information on my research (under construction). If anything triggers your attention, feel free to contact me.
Abstract Quantum processors rely on classical electronic controllers to manipulate and read out the state of quantum bits (qubits). As the performance of the quantum processor improves, nonidealities in the classical controller can become the performance bottleneck for the whole quantum computer. To prevent such limitation, this paper presents a systematic study of the impact of the classical electrical signals on the qubit fidelity. All operations, i.e., single-qubit rotations, two-qubit gates, and readout, are considered, in the presence of errors in the control electronics, such as static, dynamic, systematic, and random errors. Although the presented study could be extended to any qubit technology, it currently focuses on single-electron spin qubits, because of several advantages, such as purely electrical control and long coherence times, and for their potential for large-scale integration. As a result of this study, detailed electrical specifications for the classical control electronics for a given qubit fidelity can be derived. We also discuss how qubit fidelity is affected by the limited performance of the general-purpose room-temperature equipment typically employed to control the few qubits available today. Ultimately, we show that tailor-made electronic controllers can achieve significantly lower power, cost, and size, as required to support the scaling up of quantum computers.
Coming Thursday, June 27th, at 10:00 AM ET, I’ll give a webinar on “Cryogenic CMOS Interfaces for Large-Scale Quantum Computers”. The webinar is organized by the IEEE Solid-State Circuit Society and you can register to attend here.
There will be the opportunity to ask questions. I hope many of you will join!
My article in the “News and views” section of Nature Electronics has just been published on-line. You can find it freely available here: https://rdcu.be/bG4sI.
In this piece, titled “Scalable read-out schemes for qubits“, I comment on the latest results by Dr. Fernando Gonzalez-Zalba at Hitachi Cambridge Laboratory on selective DRAM-like readout of spin qubits (also published in Nature Electronics). I give my views on current state-of-the-art on electronic interfaces for solid-state quantum processors and outline the path that electrical and Quantum Engineers will have to follow to give birth to scalable quantum computers.
The work of two of my Ph.D. students has been accepted for presentation at the coming ESSCIRC/ESSDERC conferences to be held in Krakow, Poland next September. Congratulations to Job and Pascal!
Job’s work is showing how to build a voltage reference in standard CMOS that can operate over the whole ultra-wide temperature range from 4 K to 300 K. And, for the first time, we are showing significant statistical data demonstrating the accuracy of such references down to cryogenic temperature.
In the other paper by Pascal, we focus on device characterization of CMOS transistors at cryogenic temperature. We extend our prior work on cryo-CMOS mismatch by showing the characterization of transistor mismatch over a wide range of operating regimes, from strong inversion down to weak inversion. In particular, weak inversion operation is very relevant as it allows for low-power operation, as required in several power-limited cryogenic applications, such as quantum computing.
Both papers will be presented on the first day of the conference, on Tuesday morning and afternoon. See here.
- Job van Staveren, Carmina Garcia Almudever, Giordano Scappucci, Menno Veldhorst, Masoud Babaie, Edoardo Charbon, Fabio Sebastiano, “Voltage References for the Ultra-Wide Temperature Range from 4.2K to 300K in 40-nm CMOS,” to be presented at ESSCIRC 2019.
- Pascal A. ‘T Hart, Masoud Babaie, Edoardo Charbon, Andrei Vladimirescu, Fabio Sebastiano, “Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures,” to be presented at ESSDERC 2019.
This year, I organized a session on Quantum Computing at ISCAS 2019 in Japan!
The International Symposium on Circuits and Systems will be held in Sapporo, Japan, from May 26th to May 29th. The session titled “Towards Large-Scale Quantum Computers Session” will be held on May 28th at 14:50. More information here.
Six speakers from top-notch groups around the world will discuss the challenges and the research opportunities to be addressed on the path to build a quanutm computer with enough computing power to solve relevant problems, such as simulating a quantum systems like complex molecules and materials. The talks will span the whole stack of discipline required to build such a complex machine, ranging from quantum physics, thorugh electrical engineering and circuit design and up to computer architectures and quanutm compilers.
Join the session if you are in Sapporo!
A list of the papers below:
- Semiconductor spin qubits – a scalable platform for quantum computing? L. Schreiber, H. Bluhm, RWTH Aachen University, Germany
- Benefits and Challenges of Designing Cryogenic CMOS RF Circuits for Quantum Computer, M.Babaie1, M. Mehrpoo1, B. Patra1, J. Gong1, J.P.G. van Dijk1, P.A. ‘t Hart1, G. Kiene1, A. Vladimirescu1,2,3, F. Sebastiano1, E. Charbon1,4,5, 1Delft University of Technology, The Netherlands2University of California at Berkeley, U.S.,3Institut Supérieur d’Electronique de Paris, France 4EPFL, Switzerland5Intel, U.S.
- Systems Engineering of Cryogenic CMOS Electronics for Scalable Quantum Computers, C. Degenhardt1, A. Artanov1, V. Christ1, L. Geck1, C. Grewing1, A. Kruth1, D. Liebau1, P. Muralidharan1, D. Nielinger1, P. Schubert1, P. Vliex1, A. Zambanini1, and S. van Waasen1,2 1Forschungszentrum Jülich GmbH, Jülich, Germany2University of Duisburg-Essen, Germany
- Cryogenic support circuits and systems for silicon quantum computers, Torsten Lehmann, UNSW, Australia
- Quantum Accelerated Computer Architectures, L. Riesebos, X. Fu, A. A. Moueddenne, L. Lao, S. Varsamopoulos, I. Ashraf, J. van Someren, N. Khammassi, C. G. Almudever, K. Bertels, Delft University of Technology, The Netherlands
- Reducing the Overhead of Mapping Quantum Circuits to IBM Q Systems, Atsushi Matshuo, Wakaki Hattori and Shigeru Yamashita, Ritsumeikan University, Japan
The papers are already available on IEEExplore.
The title of my talk was:
“Cryogenic CMOS Interfaces for Large-Scale Quantum Computers”
I gave a brief overview of how quantum computers will change our world and gave a glimpse of how they work. But most importantly I introduced the audience to the role that electrical engineers and integrated-circuits (IC) designers have in the development of those wonderful machines. ICs operating at cryogenic temperatures will be a fundamental enabler of large-scale quantum computers!
Current quantum processors comprise only a few quantum bits, or qubits, (less than 100) and can then be directly wired to room-temperature electronics (see figure). However, quantum computers will need thousands or even millions of qubits to address relevant problems. Since it is impossible to use thousands of cables to connect the cryogenic qubits to room-temperature electronics, we must develop a cryogenic and integrated electronic interface to relieve constraints on wiring and thus enable large-scale quantum computers.
The last lectures included:
- November 6th, 2018, hosted by the SSCS Oregon Chapter, held at Intel in Hillsboro, Oregon. Described also in the IEEE Solid-State Circuits Magazine.
- December 5th, 2018, hosted by the SSCS Benelux Chapter, held at KU Leuven in Leuven, Belgium. Described also in the IEEE Solid-State Circuits Magazine.
- February 21st, 2019, hosted by the SSCS Silicon Valley Chapter, held at Texas Instruments in Santa Clara, California.
Last week we were awarded the Best IP award at the DATE 2018 (Design Automation and Test in Europe) conference in Dresden!
In this work, we presented, for the first time, a comprehensive methodology to co-design a quantum processor and its electronic interface. As a result, this methodology will enable the design of the electronic interface for scalable quantum computers, i.e. quantum computers with enough power to address relevant practical problems.
A quantum computer fundamentally comprises a quantum processor and the classical controller required to manipulate the quantum bits (qubits). To enable the design of future quantum computers comprising millions of qubits, both the classical electronic and quantum processor must be simultaneously optimized. In the proposed co‐design methodology, qubit performance can be optimized while considering practical trade‐offs in the control circuits, such as power consumption, complexity, and cost. To this end, we have developed SPINE (SPIN Emulator), a toolset enabling the co-simulation of qubits (single‐electron spin qubits in the current implementation) and standard electronics. SPINE can run in Matlab or as a stand-alone C++ application, but also, more interestingly, its VerilogA implementation can be integrated into Cadence, the standard platform for integrated circuit design. As a result, the proposed toolset will be the basis for future electronic designers aiming to build the electronic interface for future scalable quantum computers.
A practical application of this toolset can be found in our new work posted on arXiv: The impact of classical control electronics on qubit fidelity.
The paper on the DATE website:
Great news! NWO awarded an Open Technology Program grant to a team of PI comprising Carmina Almudever, Giordano Scapucci, Menno Veldhorst, and myself, all from TU Delft.
Quantum computers hold the promise to solve problems that are intractable even by the most powerful supercomputers. With a budget of 1.2 M€ and over the span of 5 years, we will investigate how to build a practical quantum computer, and move from the current lab prototypes towards quantum computers with the capability to solve real-life problems. Building on the expertise of a multi-disciplinary team, we will address the challenges of building a large-scale quantum computer by attacking the problems at several levels, ranging from material engineering and quantum operations up to cryogenic control electronics and computer architecture. Fats progress will be facilitated by collaborating with industrial partners: Intel, the world-leading computing company, that will contribute to the fabrication of large qubit arrays, and Bluefors, leader in cryogenic refrigeration, that will participate in the development and deployment of cryogenic electronics to interface with the qubits.
Stay tuned to hear about the progress! And drop a message if you are interested to participate in this research journey as a Ph.D. student!
The Distinguished Lecturer program of the IEEE Solid-State Circuit Society (SSCS) provides world-renowned experts in the field of integrated circuits (IC) to give lectures and seminars at regional and local venues around the world. The aim is to educate and spread knowledge on a wide range of topics focusing on state-of-the-art IC technology.
I am very glad to participate in this program, and I can’t wait to take the chance to spread the word about research topics close to my heart. To this extent, I am impatient to give these talks about cryogenic CMOS electronics for quantum computation and fully-integrated references:
- Towards Large-Scale Quantum computers: Cryogenic CMOS for Scalable Quantum Computation
- To XTAL or not to XTAL: the quest for fully integrated frequency references
- References for smart sensors
To arrange a visit in the context of the SSCS DL program, you can contact me directly or visit the SSCL DL website.
Recently, Rosario and I wrote a popular-science article on cryo-CMOS circuits for quantum computing (and other cool applications). It was published in the last edition of Maxwell, the magazine of the Electrical Engineering study association (ETV) of the TU Delft. You can find it here: