New quantum chip fabricated by intel

Check out the latest developements in the Intel-QuTech collaboration:


Intel fabricated and packaged a 17-qubit superconducting quantum processor!


This year, we will have contributiuons both at ESSCIRC and at ESSDERC in Leuven:

  • M. Incandela, L. Song, H. Homulle, F. Sebastiano, E. Charbon, and A. Vladimirescu, “Nanometer CMOS Characterization and Compact Modeling at Deep-Cryogenic Temperatures,” ESSDERC 2017 – European Solid-State Device Research Conference, Leuven, Belgium, 11 – 14 Sep. 2017.
  • Pedalà, Ç. Gürleyük, S. Pan, F. Sebastiano, and K.A.A. Makinwa, “A Frequency-Locked Loop Based on an Oxide Electrothermal Filter in Standard CMOS,” ESSCIRC 2017 – European Solid-State Circuit Conference, Leuven, Belgium, 11 – 14 Sep. 2017.

Silicon Quantum Information Processing 2017

I will give an invited talk at SiQIP 2017 with title “Cryo-CMOS Electronics for Scalable Quantum Computing” in Lancaster in September.

2 presentations + poster at the Silicon Quantum Electronics Workshop

Coming August, my group will have several contributions at the Silicon Quantum Electronics Workshop in Hillsboro (OR). This is the reference workshop for the community working on silicon qubits, i.e. basically spin qubits.

We will have 2 presentations:

  • Jeroen van Dijk: Trade-offs in engineering a scalable cryogeni controller for solid-state spin-qubits
  • Bishnu Patra: Cryogenic frequency synthesis for qubit control: Analysis and Design

and several posters:

  • Rosario M. Incandela, Edoardo Charbon, Fabio Sebastiano: A 7-K noise temperature cryogenic CMOS LNA for scalable RF readout of spin qubits
  • M. Mehrpoo, F. Sebastiano, E. Charbon, M. Babaie: Design Considerations of Cryo-RFICs for Superconducting Qubits Readout
  • Andrea Ruffino, Masoud Babaie, Fabio Sebastiano, Edoardo Charbon: Cryo-CMOS circulators for spin and superconducting qubits

Cryo-CMOS at DAC 2017

I have been invited at DAC (Design Automation Conference) to give a talk on our work on cryo-CMOS for quantum computing. In particular, I will focus both on my group’s effort in design tools that can enable the design of cryogenic circuits for quantum computers, and on what the design automation industry will have to do to make quantum computers possible.

Cryo-CMOS at ISSCC 2017

Our paper “Cryo-CMOS Circuits and Systems for Scalable Quantum Computing” is to be presented at ISSCC 2017!

We will show our first results on cryogenic circuits fabricated in standard CMOS technologies for interfacing quantum processors, and we will do that at the top conference for the presentatin of advances in integrated circuits!

Short course at ISSCC in San Francisco

It’s again time for the International Solid State Circuit Conference in San Francisco (Jan. 31 – Feb. 4th)!

This year I will participate in teaching the ISSCC short course with a talk on Frequency references for Internet-of-Everything. The so-called Internet-of-(Every)thing requires radios that are small, cheap and energy efficient. A required component of such radios is the frequency reference. The frequency reference enables both time synchronization, for duty-cycling and thus saving power, and the selection of the right band for wireless communication. Since miniaturization is a key aspect of such application to keep low cost and minimum size, the frequency reference cannot use a standard quartz crystal but must be fully integrated. I will present an overview of the alternatives to implement those references (such as RC oscillators, LC oscillator, ring oscillators,…) and describe the main sources of inaccuracy and how to handle them, for example through reducing supply sensitivity and adopting temperature compensation.

Moreover, I will give a talk on Self-Calibration Techniques for Precision Sensing Applications within the forum “Data-Converter Calibration and Dynamic-Matching Techniques”, and two papers that I co-authored will be presented in the “Oversampling data converters” (on an energy-efficient high-resolution ΣΔ converter) and in the “Sensor and displays” (on a very-small-area temperature sensor) sessions [1, 2]. The temperature sensor will also be demonstrated during one of the demo sessions.

Take a look at the Advanced ISSCC 2016 program!


[1] [doi] U. Sönmez, F. Sebastiano, and K. A. A. Makinwa, “1650µm² Thermal-Diffusivity Sensors with Inaccuracies Down to ±0.75$^\circ$C in 40nm CMOS,” in International Solid-state Circuits Conference Digest of Technical Papers, San Francisco, CA, 2016, pp. 206-207.
author={Ugur Sönmez and Fabio Sebastiano and Kofi A.A. Makinwa},
booktitle={International Solid-state Circuits Conference Digest of Technical Papers},
address="San Francisco, CA",
title="1650µm² Thermal-Diffusivity Sensors with Inaccuracies Down to ±0.75$^\circ$C in 40nm {CMOS}",
abstract={This work presents a thermal diffusivity (TD) sensor realized in nanometer (40nm) CMOS that demonstrates that the performance of such sensors continues to improve with scaling. Without trimming, the sensor achieves 1.4C (3s) inaccuracy from -40 to 125C, which is a 5 improvement over previous (non-TD) sensors intended for thermal monitoring. This improves to 0.75C (3s) after a single-point trim, a level of accuracy that previously would have required two-point trimming. Furthermore, it operates from supply voltages as low as 0.9V, and occupies only 1650 m2, making it one of the smallest smart temperature sensors reported to date. These advances are enabled by the use of a phase-calibration scheme and a highly digital phase-domain ?S ADC.},
keywords={CMOS integrated circuits;calibration;delta-sigma modulation;temperature sensors;thermal diffusivity;CMOS;digital phase-domain ?S ADC;phase-calibration scheme;scaling;single-point trim;size 40 nm;smart temperature sensors;temperature -40 degC to 125 degC;thermal monitoring;thermal-diffusivity sensors;CMOS integrated circuits;Monitoring;Radiation detectors;Temperature measurement;Temperature sensors},
[2] [doi] B. Gönen, F. Sebastiano, R. and Veldhoven, and K. A. A. Makinwa, “A 1.65mW 0.16mm² Dynamic Zoom-ADC with 107.5dB DR in 20kHz BW,” in International Solid-state Circuits Conference Digest of Technical Papers, San Francisco, CA, 2016, pp. 282-283.
author={Burak Gönen and Fabio Sebastiano and and Robert.van Veldhoven and Kofi A.A. Makinwa},
booktitle={International Solid-state Circuits Conference Digest of Technical Papers},
address="San Francisco, CA",
title="A 1.65m{W} 0.16mm² Dynamic {Zoom-ADC with 107.5dB DR in 20kHz BW}",
abstract={Audio codecs for automotive applications and smartphones require up to five stereo channels to achieve effective acoustic noise and echo cancellation, thus demanding ADCs with low power and minimal die area. Zoom-ADCs should be well suited for such applications, since they combine compact and energy-efficient SAR ADCs with low-distortion ?S ADCs to simultaneously achieve high energy efficiency, small die area, and high linearity [1,2]. However, previous implementations were limited to the conversion of quasi-static signals, since the two ADCs were operated sequentially, with a coarse SAR conversion followed by, a much slower, fine ?S conversion. This work describes a zoom-ADC with a 20kHz bandwidth, which achieves 107.5dB DR and 104.4dB SNR while dissipating 1.65mW and occupying 0.16mm2. A comparison with recent state-of-the-art ADCs with similar resolution and bandwidth [3-7] shows that the ADC achieves significantly improved energy and area efficiency. These advances are enabled by the use of concurrent fine and coarse conversions, dynamic error-correction techniques, and an inverter-based OTA.},
keywords={codecs;delta-sigma modulation;energy conservation;error correction;invertors;operational amplifiers;SNR;acoustic noise;audio codec;automotive application;bandwidth 20 kHz;dynamic zoom-ADC;echo cancellation;energy-efficient SAR ADC;error-correction technique;inverter-based OTA;low-distortion ?S ADC;operational transconductance amplifier;power 1.65 mW;quasistatic signal;signal-noise ratio;smartphone;stereo channel;successive approximation register analog-digital converter;Bandwidth;Capacitors;Energy efficiency;Linearity;Modulation;Solid state circuits;Vehicle dynamics},

Intel invests $50m in TU Delft to build an effective quantum computer

Read the press releases from TU Delft and Intel:

TU Delft: QuTech quantum institute enters into collaboration with Intel.

Intel: Intel Invests US$50 Million to Advance Quantum Computing

And the comment of Intel CEO Brian Krzanich: The Promise of Quantum Computing

The TU Delft team with the Intel representatives.

The TU Delft team with the Intel representatives.