Jeroen van Dijk (left) receiving the Best IP award at DATE 2018 (copyright: DATE 2018).
Last week we were awarded the Best IP award at the DATE 2018 (Design Automation and Test in Europe) conference in Dresden!
In this work, we presented, for the first time, a comprehensive methodology to co-design a quantum processor and its electronic interface. As a result, this methodology will enable the design of the electronic interface for scalable quantum computers, i.e. quantum computers with enough power to address relevant practical problems.
A quantum computer fundamentally comprises a quantum processor and the classical controller required to manipulate the quantum bits (qubits). To enable the design of future quantum computers comprising millions of qubits, both the classical electronic and quantum processor must be simultaneously optimized. In the proposed co‐design methodology, qubit performance can be optimized while considering practical trade‐offs in the control circuits, such as power consumption, complexity, and cost. To this end, we have developed SPINE (SPIN Emulator), a toolset enabling the co-simulation of qubits (single‐electron spin qubits in the current implementation) and standard electronics. SPINE can run in Matlab or as a stand-alone C++ application, but also, more interestingly, its VerilogA implementation can be integrated into Cadence, the standard platform for integrated circuit design. As a result, the proposed toolset will be the basis for future electronic designers aiming to build the electronic interface for future scalable quantum computers.
A practical application of this toolset can be found in our new work posted on arXiv: The impact of classical control electronics on qubit fidelity.
The announcement on the DATE website
The paper on the DATE website:
Great news! NWO awarded an Open Technology Program grant to a team of PI comprising Carmina Almudever, Giordano Scapucci, Menno Veldhorst, and myself, all from TU Delft.
Quantum computers hold the promise to solve problems that are intractable even by the most powerful supercomputers. With a budget of 1.2 M€ and over the span of 5 years, we will investigate how to build a practical quantum computer, and move from the current lab prototypes towards quantum computers with the capability to solve real-life problems. Building on the expertise of a multi-disciplinary team, we will address the challenges of building a large-scale quantum computer by attacking the problems at several levels, ranging from material engineering and quantum operations up to cryogenic control electronics and computer architecture. Fats progress will be facilitated by collaborating with industrial partners: Intel, the world-leading computing company, that will contribute to the fabrication of large qubit arrays, and Bluefors, leader in cryogenic refrigeration, that will participate in the development and deployment of cryogenic electronics to interface with the qubits.
Stay tuned to hear about the progress! And drop a message if you are interested to participate in this research journey as a Ph.D. student!
Project description on the NWO website
Press release on QuTech website
The project Principal Investigators (from left to right): Menno Veldhorst, Giordano Scappucci, Fabio Sebastiano, and Carmina Almudever.
Photo credits: Guus Schoonewille.
The Distinguished Lecturer program of the IEEE Solid-State Circuit Society (SSCS) provides world-renowned experts in the field of integrated circuits (IC) to give lectures and seminars at regional and local venues around the world. The aim is to educate and spread knowledge on a wide range of topics focusing on state-of-the-art IC technology.
I am very glad to participate in this program, and I can’t wait to take the chance to spread the word about research topics close to my heart. To this extent, I am impatient to give these talks about cryogenic CMOS electronics for quantum computation and fully-integrated references:
- Towards Large-Scale Quantum computers: Cryogenic CMOS for Scalable Quantum Computation
- To XTAL or not to XTAL: the quest for fully integrated frequency references
- References for smart sensors
To arrange a visit in the context of the SSCS DL program, you can contact me directly or visit the SSCL DL website.
List of Distinguished Lecturer of the IEEE Solid-State Circuit Society
Recently, Rosario and I wrote a popular-science article on cryo-CMOS circuits for quantum computing (and other cool applications). It was published in the last edition of Maxwell, the magazine of the Electrical Engineering study association (ETV) of the TU Delft. You can find it here:
Designing a quantum computer is not an easy task. Recently, we developed a methodology (and the relative tools) to co-design electronic circuits and quantum bits (qubits).
It will be presented at the DATE 2018 conference (Design, Automation and Test in Europe) in March in Dresden (Germany).
Check out our work if you want to simulate qubits in Cadence next to your CMOS circuit:
- Jeroen van Dijk, Andrei Vladimirescu, Masoud Babaie, Edoardo Charbon, Fabio Sebastiano, “A Co-design Methodology for Scalable Quantum Processors and their Classical Electronic Interface”
The following 2 papers have been accepted for presenation at the 2018 International Solid-State Circuits Conference (ISSCC) (a.k.a. the chip Olympics)!
- Ç. Gürleyük, L. Pedalà, F. Sebastiano, K. A. A. Makinwa, “A CMOS Dual-RC Frequency Reference with ±250ppm Inaccuracy from -45°C to 85°C”
- S. Karmakar, B. Gönen, F. Sebastiano, R. Van Veldhoven, K. A. A. Makinwa, “A 280μW Dynamic-Zoom ADC with 120dB DR and 118dB SNDR in 1kHz BW”
Check out the ISSCC 2018 technical program
Check out the latest developements in the Intel-QuTech collaboration:
Intel fabricated and packaged a 17-qubit superconducting quantum processor!
This year, we will have contributiuons both at ESSCIRC and at ESSDERC in Leuven:
- M. Incandela, L. Song, H. Homulle, F. Sebastiano, E. Charbon, and A. Vladimirescu, “Nanometer CMOS Characterization and Compact Modeling at Deep-Cryogenic Temperatures,” ESSDERC 2017 – European Solid-State Device Research Conference, Leuven, Belgium, 11 – 14 Sep. 2017.
- Pedalà, Ç. Gürleyük, S. Pan, F. Sebastiano, and K.A.A. Makinwa, “A Frequency-Locked Loop Based on an Oxide Electrothermal Filter in Standard CMOS,” ESSCIRC 2017 – European Solid-State Circuit Conference, Leuven, Belgium, 11 – 14 Sep. 2017.
I will give an invited talk at SiQIP 2017 with title “Cryo-CMOS Electronics for Scalable Quantum Computing” in Lancaster in September.
Coming August, my group will have several contributions at the Silicon Quantum Electronics Workshop in Hillsboro (OR). This is the reference workshop for the community working on silicon qubits, i.e. basically spin qubits.
We will have 2 presentations:
- Jeroen van Dijk: Trade-offs in engineering a scalable cryogeni controller for solid-state spin-qubits
- Bishnu Patra: Cryogenic frequency synthesis for qubit control: Analysis and Design
and several posters:
- Rosario M. Incandela, Edoardo Charbon, Fabio Sebastiano: A 7-K noise temperature cryogenic CMOS LNA for scalable RF readout of spin qubits
- M. Mehrpoo, F. Sebastiano, E. Charbon, M. Babaie: Design Considerations of Cryo-RFICs for Superconducting Qubits Readout
- Andrea Ruffino, Masoud Babaie, Fabio Sebastiano, Edoardo Charbon: Cryo-CMOS circulators for spin and superconducting qubits