Authors:

ALLBabaieBreemsBruschiButtiCharbonDragoErsoyFanFerrariGonenHomulleHuijsingIncandelaLeenaertsMakinwaNautaPiottoPratiQuanReimannRooversSonmezvan

Type:

ALLJournal paperConference paperBookPatent

2019

• M. Mehrpoo, B. Patra, J. Gong, P. A. ‘. Hart, J. P. G. van Dijk, H. Homulle, G. Kiene, A. Vladimirescu, F. Sebastiano, E. Charbon, and M. Babaie, “Benefits and Challenges of Designing Cryogenic CMOS RF Circuits for Quantum Computers,” in 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, pp. 1-5.
  [Abstract] [Bibtex]
  

  Accurate and low-noise generation and amplification of microwave signals are required for the manipulation and readout of quantum bits (qubits). A fault-tolerant quantum computer operates at deep cryogenic temperatures (i.e., < 100mK) and requires thousands of qubits for running practical quantum algorithms. Consequently, CMOS radio-frequency (RF) integrated circuits operating at cryogenic temperatures down to 4 K (Cryo-CMOS) offer a higher level of system integration and scalability for future quantum computers. In this paper, we extensively discuss the role, benefits, and constraints of Cryo-CMOS for qubits control and readout. The main characteristics of the CMOS transistors and their impacts on RF circuit designs are described. Furthermore, opportunities and challenges of low noise RF signal generation and amplification are investigated.

  @INPROCEEDINGS{mine:iscas_2019_milad,
  author={M. {Mehrpoo} and B. {Patra} and J. {Gong} and P. A. '. {Hart} and J. P. G. {van Dijk} and H. {Homulle} and G. {Kiene} and A. {Vladimirescu} and F. {Sebastiano} and E. {Charbon} and M. {Babaie}},
  booktitle={2019 IEEE International Symposium on Circuits and Systems (ISCAS)},
  title={Benefits and Challenges of Designing Cryogenic CMOS RF Circuits for Quantum Computers},
  year={2019},
  volume={},
  number={},
  pages={1-5},
  abstract={Accurate and low-noise generation and amplification of microwave signals are required for the manipulation and readout of quantum bits (qubits). A fault-tolerant quantum computer operates at deep cryogenic temperatures (i.e., < 100mK) and requires thousands of qubits for running practical quantum algorithms. Consequently, CMOS radio-frequency (RF) integrated circuits operating at cryogenic temperatures down to 4 K (Cryo-CMOS) offer a higher level of system integration and scalability for future quantum computers. In this paper, we extensively discuss the role, benefits, and constraints of Cryo-CMOS for qubits control and readout. The main characteristics of the CMOS transistors and their impacts on RF circuit designs are described. Furthermore, opportunities and challenges of low noise RF signal generation and amplification are investigated.},
  keywords={Qubit;Radio frequency;Cryogenics;Temperature;Computers;Superconducting device noise},
  doi={10.1109/ISCAS.2019.8702452},
  ISSN={2158-1525},
  month={May},}

• J. v. Dijk, A. Vladimirescu, M. Babaie, E. Charbon, and F. Sebastiano, "SPINE (SPIN Emulator) - A Quantum-Electronics Interface Simulator," in 2019 IEEE 8th International Workshop on Advances in Sensors and Interfaces (IWASI), 2019, pp. 23-28.
  [Abstract] [Bibtex]
  

  A quantum computer comprises a quantum processor and the associated control electronics used to manipulate the qubits at the core of a quantum processor. CMOS circuits placed close to the quantum bits and operating at cryogenic temperatures offer the best solution for the control of millions of qubits. The performance requirements of the electronics are very stringent and its design requires the simultaneous optimization of both the circuits and the quantum system. This paper presents the SPINE (SPIN Emulator) toolset for the co-design and co-optimization of electronic/quantum systems. It comprises a SPICE simulator enhanced with a Verilog-A model based on a Hamiltonian solver emulating the quantum behavior of single-electron spin qubits. A co-design methodology is proposed to derive on the one hand the specifications of the electrical signals to be applied to and captured from the qubits, and to ensure on the other hand, the compliance of the electronics in generating the required signals. This methodology results in an optimized qubit performance while considering practical trade-offs in the control circuits, such as power consumption, complexity and cost as proven by a practical design example.

  @INPROCEEDINGS{mine:iwasi_spine_2019,
  author={J. v. {Dijk} and A. {Vladimirescu} and M. {Babaie} and E. {Charbon} and F. {Sebastiano}},
  booktitle={2019 IEEE 8th International Workshop on Advances in Sensors and Interfaces (IWASI)},
  title={SPINE (SPIN Emulator) - A Quantum-Electronics Interface Simulator},
  year={2019},
  volume={},
  number={},
  pages={23-28},
  abstract={A quantum computer comprises a quantum processor and the associated control electronics used to manipulate the qubits at the core of a quantum processor. CMOS circuits placed close to the quantum bits and operating at cryogenic temperatures offer the best solution for the control of millions of qubits. The performance requirements of the electronics are very stringent and its design requires the simultaneous optimization of both the circuits and the quantum system. This paper presents the SPINE (SPIN Emulator) toolset for the co-design and co-optimization of electronic/quantum systems. It comprises a SPICE simulator enhanced with a Verilog-A model based on a Hamiltonian solver emulating the quantum behavior of single-electron spin qubits. A co-design methodology is proposed to derive on the one hand the specifications of the electrical signals to be applied to and captured from the qubits, and to ensure on the other hand, the compliance of the electronics in generating the required signals. This methodology results in an optimized qubit performance while considering practical trade-offs in the control circuits, such as power consumption, complexity and cost as proven by a practical design example.},
  keywords={cryogenics;quantum computing;quantum entanglement;quantum optics;SPICE;quantum processor;CMOS circuits;quantum bits;performance requirements;simultaneous optimization;SPINE toolset;SPIN Emulator;SPICE simulator;quantum behavior;single-electron spin qubits;co-design methodology;optimized qubit performance;control circuits;practical design example;quantum-electronics interface simulator;quantum computer;control electronics;cryogenic temperatures;electronic/quantum systems;Verilog-A model;Hamiltonian solver;electrical signals;power consumption;Qubit;Integrated circuit modeling;Computational modeling;Computer architecture;Tools;Semiconductor device modeling;Quantum computing;spin qubit;Hamiltonian simulation;co-simulation;co-design methodology;classical electronic interface},
  doi={10.1109/IWASI.2019.8791334},
  ISSN={},
  month={June},}

• A. Ruffino, Y. Peng, F. Sebastiano, M. Babaie, and E. Charbon, "A 6.5-GHz Cryogenic All-Pass Filter Circulator in 40-nm CMOS for Quantum Computing Applications," in 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2019, pp. 107-110.
  [Abstract] [Bibtex]
  

  Cryogenic solid-state quantum processors require classical control and readout electronics; to achieve compactness and scalability, cryogenic integrated circuits have been recently proposed for this goal. Circulators are widely used in readout circuits, however they are typically discrete bulky devices, thus preventing miniaturization. To address this issue, we propose a fully integrated 40-nm CMOS 6.5-GHz circulator operating from 300 K to 4.2 K. At 300 K, it achieves a 2.2-dB insertion loss, an 18-dB isolation, and a 2.4-dB noise figure over the 1-dB bandwidth from 5.6 GHz to 7.4 GHz, with a core power of only 2.5 mW. This improves to 2.1 mW core power at 4.2 K, while showing 1.3-dB insertion loss and 17-dB isolation over the 1-dB bandwidth from 5.8 GHz to 7.6 GHz. The circuit achieves a record-low core power and a 1.6× wider fractional bandwidth than the state-of-the-art, thus allowing its use for multiple channels in power-constrained cryogenic refrigerators. These advances are enabled by a fully-passive architecture based on LC all-pass filters, allowing the use of a lower clock frequency than in prior art.

  @INPROCEEDINGS{mine:rfic_2019_ruffino,
  author={A. {Ruffino} and Y. {Peng} and F. {Sebastiano} and M. {Babaie} and E. {Charbon}},
  booktitle={2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)},
  title={A 6.5-GHz Cryogenic All-Pass Filter Circulator in 40-nm CMOS for Quantum Computing Applications},
  year={2019},
  volume={},
  number={},
  pages={107-110},
  abstract={Cryogenic solid-state quantum processors require classical control and readout electronics; to achieve compactness and scalability, cryogenic integrated circuits have been recently proposed for this goal. Circulators are widely used in readout circuits, however they are typically discrete bulky devices, thus preventing miniaturization. To address this issue, we propose a fully integrated 40-nm CMOS 6.5-GHz circulator operating from 300 K to 4.2 K. At 300 K, it achieves a 2.2-dB insertion loss, an 18-dB isolation, and a 2.4-dB noise figure over the 1-dB bandwidth from 5.6 GHz to 7.4 GHz, with a core power of only 2.5 mW. This improves to 2.1 mW core power at 4.2 K, while showing 1.3-dB insertion loss and 17-dB isolation over the 1-dB bandwidth from 5.8 GHz to 7.6 GHz. The circuit achieves a record-low core power and a 1.6× wider fractional bandwidth than the state-of-the-art, thus allowing its use for multiple channels in power-constrained cryogenic refrigerators. These advances are enabled by a fully-passive architecture based on LC all-pass filters, allowing the use of a lower clock frequency than in prior art.},
  keywords={all-pass filters;CMOS integrated circuits;cryogenic electronics;integrated optoelectronics;microwave circulators;microwave photonics;optical circulators;optical filters;optical losses;quantum computing;quantum optics;readout electronics;insertion loss;noise figure;core power;cryogenic all-pass filter circulator;cryogenic solid-state quantum processors;classical control;fully integrated 40-nm CMOS 6.5-GHz circulator;ractional bandwidth;fully-passive architecture;LC all-pass filters;readout circuits;cryogenic integrated circuits;quantum computing applications;power-constrained cryogenic refrigerators;18-dB isolation;power 2.5 mW;power 2.1 mW;temperature 4.2 K to 300.0 K;frequency 5.6 GHz to 7.4 GHz;frequency 5.8 GHz to 7.6 GHz;size 40 nm;Circulators;Qubit;Clocks;Bandwidth;Scattering parameters;Cryogenics;Insertion loss;Cryo-CMOS;circulator;qubit;spin qubit;superconducting qubit;qubit readout;quantum computing},
  doi={10.1109/RFIC.2019.8701836},
  ISSN={},
  month={June},}

• P. A. 't Hart, M. Babaie, E. Charbon, A. Vladimirescu, and F. Sebastiano, "Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures," in 2019 49th European Solid-State Device Research Conference (ESSDERC), 2019.
  [Abstract] [Bibtex]
  

  Cryogenic device models are essential for the reliable design of the cryo-CMOS interface that enables large-scale quantum computers. In this paper, mismatch characterization and modeling of a 40-nm bulk CMOS process over the 4:2–300 K temperature range is studied, towards an all-operating-region mismatch model. An overall increase of variability is shown, in particular in the subthreshold region at cryogenic temperatures due to a dramatic increase of the subthreshold slope mismatch. Mismatch in strong inversion is modeled by the Croon model while the weak-inversion region is modeled by taking subthreshold slope variability into account. This results in the first model capable of predicting mismatch over the whole range of operating regions and temperatures.

  @INPROCEEDINGS{mine:essderc2019_pascal,
  author={P. A. {'t Hart} and M. {Babaie} and E. {Charbon} and A. {Vladimirescu} and F. {Sebastiano}},
  booktitle={2019 49th European Solid-State Device Research Conference (ESSDERC)},
  title={Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures},
  year={2019},
  volume={},
  number={},
  pages={},
  abstract={Cryogenic device models are essential for the reliable design of the cryo-CMOS interface that enables large-scale quantum computers. In this paper, mismatch characterization and modeling of a 40-nm bulk CMOS process over the 4:2–300 K temperature range is studied, towards an all-operating-region mismatch model. An overall increase of variability is shown, in particular in the subthreshold region at cryogenic temperatures due to a dramatic increase of the subthreshold slope mismatch. Mismatch in strong inversion is modeled by the Croon model while the weak-inversion region is modeled by taking subthreshold slope variability into account. This results in the first model capable of predicting mismatch over the whole range of operating regions and temperatures.},
  doi={},
  month={Sep.},}

• J. van Staveren, G. C. Almudever, G. Scappucci, M. Veldhorst, M. Babaie, E. Charbon, and F. Sebastiano, "Voltage References for the Ultra-Wide Temperature Range from 4.2K to 300K in 40-nm CMOS," in 2019 49th European Solid-State Device Research Conference (ESSDERC), 2019.
  [Abstract] [Bibtex]
  

  This paper presents a family of voltage references in standard 40-nm CMOS that exploits the temperature dependence of dynamic-threshold MOS, NMOS and PMOS transistors in weak inversion to enable operation over the ultra-wide temperature range from 4.2K to 300 K. The proposed references achieve a temperature drift below 436 ppm/K over a statistically significant number of samples after a single-point trim and a supply regulation better than 1.7 %/V from a a supply as low as 0.99 V. These results demonstrate, for the first time, the generation of PVT-independent voltages over an ultra-wide temperature range using sub-1-V nanometer CMOS circuits, thus enabling the use of the proposed references in harsh environments, such as in space and quantum-computing applications.

  @INPROCEEDINGS{mine:essCCIRC2019_Job,
  author={J. van Staveren and C. Garcia Almudever and G. Scappucci and M. Veldhorst and M. {Babaie} and E. {Charbon} and F. {Sebastiano}},
  booktitle={2019 49th European Solid-State Device Research Conference (ESSDERC)},
  title={Voltage References for the Ultra-Wide Temperature Range from 4.2K to 300K in 40-nm CMOS},
  year={2019},
  volume={},
  number={},
  pages={},
  abstract={This paper presents a family of voltage references in standard 40-nm CMOS that exploits the temperature dependence of dynamic-threshold MOS, NMOS and PMOS transistors in weak inversion to enable operation over the ultra-wide temperature range from 4.2K to 300 K. The proposed references achieve a temperature drift below 436 ppm/K over a statistically significant number of samples after a single-point trim and a supply regulation better than 1.7 %/V from a a supply as low as 0.99 V. These results demonstrate, for the first time, the generation of PVT-independent voltages over an ultra-wide temperature range using sub-1-V nanometer CMOS circuits, thus enabling the use of the proposed references in harsh environments, such as in space and quantum-computing applications.},
  doi={},
  month={Sep.},}

• J. P. G. van Dijk, E. Charbon, and F. Sebastiano, "The electronic interface for quantum processors," Microprocessors and Microsystems, vol. 66, pp. 90-101, 2019.
  [Abstract] [Bibtex]
  

  Quantum computers can potentially provide an unprecedented speed-up with respect to traditional computers. However, a significant increase in the number of quantum bits (qubits) and their performance is required to demonstrate such quantum supremacy. While scaling up the underlying quantum processor is extremely challenging, building the electronics required to interface such large-scale processor is just as relevant and arduous. This paper discusses the challenges in designing a scalable electronic interface for quantum processors. To that end, we discuss the requirements dictated by different qubit technologies and present existing implementations of the electronic interface. The limitations in scaling up such state-of-the-art implementations are analyzed, and possible solutions to overcome those hurdles are reviewed. The benefits offered by operating the electronic interface at cryogenic temperatures in close proximity to the low-temperature qubits are discussed. Although several significant challenges must still be faced by researchers in the field of cryogenic control for quantum processors, a cryogenic electronic interface appears the viable solution to enable large-scale quantum computers able to address world-changing computational problems.

  @ARTICLE{mine:micpro2019,
  author={Jeroen P. G. {van Dijk} and E. {Charbon} and Fabio {Sebastiano}},
  journal={Microprocessors and Microsystems},
  title={The electronic interface for quantum processors},
  year={2019},
  volume={66},
  pages={90-101},
  abstract={Quantum computers can potentially provide an unprecedented speed-up with respect to traditional computers. However, a significant increase in the number of quantum bits (qubits) and their performance is required to demonstrate such quantum supremacy. While scaling up the underlying quantum processor is extremely challenging, building the electronics required to interface such large-scale processor is just as relevant and arduous. This paper discusses the challenges in designing a scalable electronic interface for quantum processors. To that end, we discuss the requirements dictated by different qubit technologies and present existing implementations of the electronic interface. The limitations in scaling up such state-of-the-art implementations are analyzed, and possible solutions to overcome those hurdles are reviewed. The benefits offered by operating the electronic interface at cryogenic temperatures in close proximity to the low-temperature qubits are discussed. Although several significant challenges must still be faced by researchers in the field of cryogenic control for quantum processors, a cryogenic electronic interface appears the viable solution to enable large-scale quantum computers able to address world-changing computational problems.},
  keywords={Quantum computingQuantum bit (qubit)ElectronicsCMOSCryo-CMOSCryogenics},
  doi={10.1016/j.micpro.2019.02.004},
  month={Apr},}

2018

• &. Gürleyük, L. Pedalá, F. Sebastiano, and K. A. A. Makinwa, "A CMOS Dual-RC frequency reference with ±250ppm inaccuracy from -45 C to 85 C," in 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, pp. 54-56.
  [Bibtex]

  @INPROCEEDINGS{mine:isscc_2018_frequency_reference_cagri,
  author={Ç. Gürleyük and L. Pedal\'{a} and F. Sebastiano
  and K. A. A. Makinwa}, booktitle={2018 IEEE International Solid -
  State Circuits Conference - (ISSCC)}, title={A CMOS Dual-RC
  frequency reference with ±250ppm inaccuracy from -45 C to 85
  C}, year={2018}, volume={}, number={}, pages={54-56},
  keywords={Circuit stability;Frequency locked
  loops;Jitter;Oscillators;Resistors;Temperature measurement;Thermal
  stability}, doi={10.1109/ISSCC.2018.8310180}, ISSN={2376-8606},
  month={Feb},}

• S. Karmakar, B. Gönen, F. Sebastiano, V. R. Veldhoven, and K. A. A. Makinwa, "A 280 µW dynamic-zoom ADC with 120dB DR and 118dB SNDR in 1kHz BW," in 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, pp. 238-240.
  [Bibtex]

  @INPROCEEDINGS{mine:isscc_2018_zoomadc_shoubhik, author={S.
  Karmakar and B. G\"onen and F. Sebastiano and R. Van Veldhoven and
  K. A. A. Makinwa}, booktitle={2018 IEEE International Solid - State
  Circuits Conference - (ISSCC)}, title={A 280 µW dynamic-zoom
  ADC with 120dB DR and 118dB SNDR in 1kHz BW}, year={2018},
  volume={}, number={}, pages={238-240},
  keywords={Capacitors;Clocks;Dynamic
  range;Linearity;Modulation;Robustness;Signal to noise ratio},
  doi={10.1109/ISSCC.2018.8310272}, ISSN={2376-8606}, month={Feb},}

• J. van Dijk, A. Vladimirescu, M. Babaie, E. Charbon, and F. Sebastiano, "A co-design methodology for scalable quantum processors and their classical electronic interface," in 2018 Design, Automation Test in Europe Conference Exhibition (DATE), 2018, pp. 573-576.
  [Abstract] [Bibtex]
  

  A quantum computer fundamentally comprises a quantum processor and a classical controller. The classical electronic controller is used to correct and manipulate the qubits, the core components of a quantum processor. To enable quantum computers scalable to millions of qubits, as required in practical applications, the simultaneous optimization of both the classical electronic and quantum systems is needed. In this paper, a co-design methodology is proposed for obtaining an optimized qubit performance while considering practical trade-offs in the control circuits, such as power consumption, complexity, and cost. The SPINE (SPIN Emulator) toolset is introduced for the co-design and co-optimization of electronic/quantum systems. It comprises a circuit simulator enhanced with a Verilog-A model emulating the quantum behavior of single-electron spin qubits. Design examples show the effectiveness of the proposed methodology in the optimization, design and verification of a whole electronic/quantum system.

  @INPROCEEDINGS{mine:DATE2018,
  author={J. {van Dijk} and A. {Vladimirescu} and M. {Babaie} and E. {Charbon} and F. {Sebastiano}},
  booktitle={2018 Design, Automation Test in Europe Conference Exhibition (DATE)},
  title={A co-design methodology for scalable quantum processors and their classical electronic interface},
  year={2018},
  volume={},
  number={},
  pages={573-576},
  abstract={A quantum computer fundamentally comprises a quantum processor and a classical controller. The classical electronic controller is used to correct and manipulate the qubits, the core components of a quantum processor. To enable quantum computers scalable to millions of qubits, as required in practical applications, the simultaneous optimization of both the classical electronic and quantum systems is needed. In this paper, a co-design methodology is proposed for obtaining an optimized qubit performance while considering practical trade-offs in the control circuits, such as power consumption, complexity, and cost. The SPINE (SPIN Emulator) toolset is introduced for the co-design and co-optimization of electronic/quantum systems. It comprises a circuit simulator enhanced with a Verilog-A model emulating the quantum behavior of single-electron spin qubits. Design examples show the effectiveness of the proposed methodology in the optimization, design and verification of a whole electronic/quantum system.},
  keywords={circuit simulation;quantum computing;single-electron spin qubits;quantum behavior;co-optimization;control circuits;practical trade-offs;optimized qubit performance;quantum systems;classical electronic systems;simultaneous optimization;classical electronic controller;classical controller;quantum processor;quantum computer;classical electronic interface;scalable quantum processors;co-design methodology;electronic/quantum system;Program processors;Integrated circuit modeling;Quantum computing;Computational modeling;Quantum dots;Hardware design languages;C++ languages},
  doi={10.23919/DATE.2018.8342072},
  ISSN={1558-1101},
  month={March},}

• C. G. Almudever, N. Khammassi, L. Hutin, M. Vinet, M. Babaie, F. Sebastiano, E. Charbon, and K. Bertels, "Towards a scalable quantum computer," in 2018 13th International Conference on Design Technology of Integrated Systems In Nanoscale Era (DTIS), 2018, pp. 1-1.
  [Abstract] [Bibtex]
  

  A quantum machine may solve some complex problems that are intractable for even the most powerful classical computers. By exploiting quantum superposition and entanglement phenomena, quantum algorithms can achieve from polynomial to exponential speed up when compared to their best classical counterparts. A quantum computer will be a part of a heterogeneous, multi-core computer in which a classical processor will interact with several accelerators such as FPGAs, GPUs and also a quantum co-processor. Figure 1 shows the different layers of the quantum computer system stack [1]. Building such a quantum system requires contributions from different fields such as physics, electronics, computer science and computer engineering for addressing the following challenges: i) build scalable quantum chips integrating qubits with long coherence times and high-fidelity operations, ii) develop classical control electronics at possibly cryogenic temperatures and iii) create the microarchitecture as well as the software for quantum computation.

  @INPROCEEDINGS{mine:DTIS2018,
  author={C. G. {Almudever} and N. {Khammassi} and L. {Hutin} and M. {Vinet} and M. {Babaie} and F. {Sebastiano} and E. {Charbon} and K. {Bertels}},
  booktitle={2018 13th International Conference on Design Technology of Integrated Systems In Nanoscale Era (DTIS)},
  title={Towards a scalable quantum computer},
  year={2018},
  volume={},
  number={},
  pages={1-1},
  abstract={A quantum machine may solve some complex problems that are intractable for even the most powerful classical computers. By exploiting quantum superposition and entanglement phenomena, quantum algorithms can achieve from polynomial to exponential speed up when compared to their best classical counterparts. A quantum computer will be a part of a heterogeneous, multi-core computer in which a classical processor will interact with several accelerators such as FPGAs, GPUs and also a quantum co-processor. Figure 1 shows the different layers of the quantum computer system stack [1]. Building such a quantum system requires contributions from different fields such as physics, electronics, computer science and computer engineering for addressing the following challenges: i) build scalable quantum chips integrating qubits with long coherence times and high-fidelity operations, ii) develop classical control electronics at possibly cryogenic temperatures and iii) create the microarchitecture as well as the software for quantum computation.},
  keywords={quantum computing;quantum entanglement;scalable quantum computer;quantum machine;powerful classical computers;quantum superposition;entanglement phenomena;quantum algorithms;classical counterparts;multicore computer;classical processor;quantum co-processor;quantum computer system stack;quantum system;computer science;computer engineering;scalable quantum chips;classical control electronics;quantum computation;FPGA;GPU;cryogenic temperatures;Quantum computing;Cryogenics;Quantum entanglement;Buildings;Coherence;Temperature control;Microarchitecture},
  doi={10.1109/DTIS.2018.8368579},
  ISSN={},
  month={April},}

• P. A. 't Hart, J. P. G. van Dijk, M. Babaie, E. Charbon, A. Vladimirescu, and F. Sebastiano, "Characterization and Model Validation of Mismatch in Nanometer CMOS at Cryogenic Temperatures," in 2018 48th European Solid-State Device Research Conference (ESSDERC), 2018, pp. 246-249.
  [Abstract] [Bibtex]
  

  The design of cryogenic interface electronics enabling future scalable quantum computers requires the accurate characterization and modeling of nanometer CMOS processes at cryogenic temperatures. To this end, this paper presents the mismatch characterization of 40-nm bulk CMOS transistors over the temperature range from 300 K down to 4.2 K. Measured data confirm that variability increases at cryogenic temperatures, and analysis of such data proves the validity of both the Pelgrom and the Croon models, which describe the mismatch dependency on device area and bias conditions, respectively.

  @INPROCEEDINGS{mine:essderc2018_pascal,
  author={P. A. {'t Hart} and J. P. G. {van Dijk} and M. {Babaie} and E. {Charbon} and A. {Vladimirescu} and F. {Sebastiano}},
  booktitle={2018 48th European Solid-State Device Research Conference (ESSDERC)},
  title={Characterization and Model Validation of Mismatch in Nanometer CMOS at Cryogenic Temperatures},
  year={2018},
  volume={},
  number={},
  pages={246-249},
  abstract={The design of cryogenic interface electronics enabling future scalable quantum computers requires the accurate characterization and modeling of nanometer CMOS processes at cryogenic temperatures. To this end, this paper presents the mismatch characterization of 40-nm bulk CMOS transistors over the temperature range from 300 K down to 4.2 K. Measured data confirm that variability increases at cryogenic temperatures, and analysis of such data proves the validity of both the Pelgrom and the Croon models, which describe the mismatch dependency on device area and bias conditions, respectively.},
  keywords={CMOS integrated circuits;cryogenics;integrated circuit modelling;nanoelectronics;quantum computing;transistor circuits;mismatch characterization;cryogenic temperatures;Croon models;cryogenic interface electronics;nanometer CMOS processes;CMOS transistors;quantum computers;temperature 300.0 K;temperature 4.2 K;Cryogenics;MOS devices;Temperature distribution;Transistors;Standards;Semiconductor device modeling},
  doi={10.1109/ESSDERC.2018.8486859},
  ISSN={2378-6558},
  month={Sep.},}

• B. Patra, R. M. Incandela, J. P. G. van Dijk, H. A. R. Homulle, L. Song, M. Shahmohammadi, R. B. Staszewski, A. Vladimirescu, M. Babaie, F. Sebastiano, and E. Charbon, "Cryo-CMOS Circuits and Systems for Quantum Computing Applications," IEEE Journal of Solid-State Circuits, vol. 53, iss. 1, pp. 1-13, 2018.
  [Abstract] [Bibtex]
  

  A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum computers. In this paper, a cryogenic control system is proposed, along with the required specifications, for the interface of the classical electronics with the quantum processor. To prove the advantages of such a system, the functionality of key circuit blocks is experimentally demonstrated. The characteristic properties of cryo-CMOS are exploited to design a noise-canceling low-noise amplifier for spin-qubit RF-reflectometry readout and a class-F2,3 digitally controlled oscillator required to manipulate the state of qubits.

  @ARTICLE{mine:jssc_2018_cryocmos,
  author={Bishnu Patra and Rosario M. Incandela and Jeroen P. G. van Dijk and Harald A. R. Homulle and Lin Song and Mina Shahmohammadi and Robert B. Staszewski and Andrei Vladimirescu and Masoud Babaie and Fabio Sebastiano and Edoardo Charbon},
  journal={IEEE Journal of Solid-State Circuits},
  title={Cryo-CMOS Circuits and Systems for Quantum Computing Applications},
  year={2018},
  volume={53},
  number={1},
  pages={1-13},
  abstract={A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum computers. In this paper, a cryogenic control system is proposed, along with the required specifications, for the interface of the classical electronics with the quantum processor. To prove the advantages of such a system, the functionality of key circuit blocks is experimentally demonstrated. The characteristic properties of cryo-CMOS are exploited to design a noise-canceling low-noise amplifier for spin-qubit RF-reflectometry readout and a class-F2,3 digitally controlled oscillator required to manipulate the state of qubits.},
  keywords={CMOS technology;Cryogenics;Oscillators;Process control;Quantum computing;Temperature;CMOS characterization;Class-F oscillator;cryo-CMOS;low-noise amplifier (LNA);noise canceling;phase noise (PN);quantum bit (qubit);quantum computing;qubit control;single-photon avalanche diode (SPAD).},
  doi={10.1109/JSSC.2017.2737549},
  ISSN={0018-9200},
  month={Jan},}

• H. Homulle, L. Song, E. Charbon, and F. Sebastiano, "The Cryogenic Temperature Behavior of Bipolar, MOS and DTMOS Transistors in Standard CMOS," IEEE Journal of the Electron Devices Society, vol. 6, iss. 1, pp. 263-210, 2018.
  [Abstract] [Bibtex]
  

  Both CMOS bandgap voltage references and temperature sensors rely on the temperature behavior of either CMOS substrate BJTs or MOS transistors in weak inversion. Bipolar transistors are generally preferred over MOS transistors because of their lower spread. However, at deep-cryogenic temperatures, the performance of BJTs deteriorates due to a significant reduction in current gain and a substantial increase in the base resistance. On the contrary, MOS devices show more stable performance even down to 4 K, but accurate device characterization for the design of such a circuit is currently missing. We present the characterization and analysis over the temperature range from 4 K to 300 K of both substrate bipolar PNP transistors and MOS transistors in standard and dynamic threshold MOS (DTMOS) configurations implemented in a standard 0.16-um CMOS technology. These results demonstrate that employing MOS or DTMOS enables the operation of bandgap references and temperature sensors in standard CMOS technologies even at deep-cryogenic temperatures.

  @ARTICLE{mine:jeds_2018_cryo_bjt_dtmos,
  author={Harald Homulle and Lin Song and Edoardo Charbon and Fabio Sebastiano},
  journal={IEEE Journal of the Electron Devices Society},
  title={The Cryogenic Temperature Behavior of Bipolar, MOS and DTMOS Transistors in Standard CMOS},
  year={2018},
  volume={6},
  number={1},
  pages={263-210},
  abstract={Both CMOS bandgap voltage references and temperature sensors rely on the temperature behavior of either CMOS substrate BJTs or MOS transistors in weak inversion. Bipolar transistors are generally preferred over MOS transistors because of their lower spread. However, at deep-cryogenic temperatures, the performance of BJTs deteriorates due to a significant reduction in current gain and a substantial increase in the base resistance. On the contrary, MOS devices show more stable performance even down to 4 K, but accurate device characterization for the design of such a circuit is currently missing. We present the characterization and analysis over the temperature range from 4 K to 300 K of both substrate bipolar PNP transistors and MOS transistors in standard and dynamic threshold MOS (DTMOS) configurations implemented in a standard 0.16-um CMOS technology. These results demonstrate that employing MOS or DTMOS enables the operation of bandgap references and temperature sensors in standard CMOS technologies even at deep-cryogenic temperatures.},
  keywords={Current measurement;MOSFET;Photonic band gap;Standards;Substrates;Temperature measurement;Temperature sensors;CMOS;Characterization;bandgap references;cryogenics;dynamic-threshold MOS;substrate bipolar transistors;temperature sensors.},
  doi={10.1109/JEDS.2018.2798281},
  ISSN={2168-6734},
  month={jan},}

• R. M. Incandela, L. Song, H. Homulle, E. Charbon, A. Vladimirescu, and F. Sebastiano, "Characterization and Compact Modeling of Nanometer CMOS Transistors at Deep-Cryogenic Temperatures," IEEE Journal of the Electron Devices Society, vol. 6, pp. 996-1006, 2018.
  [Abstract] [Bibtex]
  

  Cryogenic characterization and modeling of two nanometer bulk CMOS technologies (0.16- $\mu \text{m}$ and 40-nm) are presented in this paper. Several devices from both technologies were extensively characterized at temperatures of 4 K and below. Based on a detailed understanding of the device physics at deep-cryogenic temperatures, a compact model based on MOS11 and PSP was developed. In addition to reproducing the device dc characteristics, the accuracy and validity of the compact models are demonstrated by comparing time- and frequency-domain simulations of complex circuits, such as a ring oscillator and a low-noise amplifier, with the measurements at 4 K.

  @ARTICLE{mine:jeds_2018,
  author={R. M. {Incandela} and L. {Song} and H. {Homulle} and E. {Charbon} and A. {Vladimirescu} and F. {Sebastiano}},
  journal={IEEE Journal of the Electron Devices Society},
  title={Characterization and Compact Modeling of Nanometer CMOS Transistors at Deep-Cryogenic Temperatures},
  year={2018},
  volume={6},
  number={},
  pages={996-1006},
  abstract={Cryogenic characterization and modeling of two nanometer bulk CMOS technologies (0.16- $\mu \text{m}$ and 40-nm) are presented in this paper. Several devices from both technologies were extensively characterized at temperatures of 4 K and below. Based on a detailed understanding of the device physics at deep-cryogenic temperatures, a compact model based on MOS11 and PSP was developed. In addition to reproducing the device dc characteristics, the accuracy and validity of the compact models are demonstrated by comparing time- and frequency-domain simulations of complex circuits, such as a ring oscillator and a low-noise amplifier, with the measurements at 4 K.},
  keywords={Integrated circuit modeling;Semiconductor device modeling;Cryogenics;MOS devices;CMOS technology;Quantum computing;Cryogenic electronics;CMOS;cryogenic;cryo-CMOS;characterization;modeling;kink;4 K;LNA},
  doi={10.1109/JEDS.2018.2821763},
  ISSN={2168-6734},
  month={},}

• S. Karmakar, B. Gönen, F. Sebastiano, R. van Veldhoven, and K. A. A. Makinwa, "A 280 µ W Dynamic Zoom ADC With 120 dB DR and 118 dB SNDR in 1 kHz BW," IEEE Journal of Solid-State Circuits, vol. 53, iss. 12, pp. 3497-3507, 2018.
  [Abstract] [Bibtex]
  

  This paper presents a dynamic zoom analog-to-digital converter for use in low-bandwidth (<;1 kHz) instrumentation applications. It employs a high-speed asynchronous successive approximation register (SAR) ADC that dynamically updates the references of a fully differential ?S ADC. Compared to previous zoom ADCs, faster reference updates relax the loop filter requirements, thus allowing the adoption of energy-efficient amplifiers. Fabricated in a 0.16-µm CMOS process, the prototype occupies 0.26 mm2 and achieves 119.1-dB peak signal-to-noise ratio (SNR), 118.1-dB peak signal-to-noise-and-distortion-ratio (SNDR), and 120.3-dB dynamic range (DR) in a 1-kHz bandwidth while consuming 280 µW. This results in a Schreier figure of merit (FoM) of 185.8 dB.

  @ARTICLE{mine:jssc2018_shoubik,
  author={S. {Karmakar} and B.{G\"onen} and F. {Sebastiano} and R. {van Veldhoven} and K. A. A.{Makinwa}},
  journal={IEEE Journal of Solid-State Circuits},
  title={A 280 µ W Dynamic Zoom ADC With 120 dB DR and 118 dB SNDR in 1 kHz BW},
  year={2018},
  volume={53},
  number={12},
  pages={3497-3507},
  abstract={This paper presents a dynamic zoom
  analog-to-digital converter for use in low-bandwidth (<;1 kHz)
  instrumentation applications. It employs a high-speed asynchronous
  successive approximation register (SAR) ADC that dynamically
  updates the references of a fully differential ?S ADC. Compared to
  previous zoom ADCs, faster reference updates relax the loop filter
  requirements, thus allowing the adoption of energy-efficient
  amplifiers. Fabricated in a 0.16-µm CMOS process, the prototype
  occupies 0.26 mm2 and achieves 119.1-dB peak signal-to-noise ratio
  (SNR), 118.1-dB peak signal-to-noise-and-distortion-ratio (SNDR),
  and 120.3-dB dynamic range (DR) in a 1-kHz bandwidth while
  consuming 280 µW. This results in a Schreier figure of merit (FoM)
  of 185.8 dB.}, keywords={amplifiers;CMOS digital integrated
  circuits;delta-sigma modulation;energy
  conservation;flip-flops;integrated circuit manufacture;low-power
  electronics;zoom analog-to-digital converter;low-bandwidth
  instrumentation applications;fully differential ?S ADC;loop filter
  requirements;energy-efficient amplifiers;dynamic zoom
  ADC;SNDR;signal-to-noise-and-distortion-ratio;high-speed
  asynchronous SAR ADC;successive approximation register;Schreier
  figure of merit;FoM;power 280.0 muW;bandwidth 1.0 kHz;size 0.16
  mum;size 0.26 mm;Signal
  resolution;Bandwidth;Linearity;Clocks;Energy
  resolution;Registers;Distance measurement;A/D
  conversion;asynchronous successive approximation register
  analog-to-digital converter;battery-powered
  applications;delta–sigma ADC;dynamic zoom ADC;inverter-based
  operational transconductance amplifier (OTA);low-power circuits},
  doi={10.1109/JSSC.2018.2865466}, ISSN={0018-9200}, month={Dec},}

• &. Gürleyük, L. Pedalá, S. Pan, F. Sebastiano, and K. A. A. Makinwa, "A CMOS Dual-RC Frequency Reference With ±200-ppm Inaccuracy From -45 °C to 85 °C," IEEE Journal of Solid-State Circuits, vol. 53, iss. 12, pp. 3386-3395, 2018.
  [Abstract] [Bibtex]
  

  This paper presents a 7-MHz CMOS RC frequency reference. It consists of a frequency-locked loop in which the output frequency of a digitally controlled oscillator (DCO) is locked to the combined phase shifts of two independent RC (Wien bridge) filters, each employing resistors with complementary temperature coefficients. The filters are driven by the DCO's output frequency and the resulting phase shifts are digitized by high-resolution phase-to-digital converters. Their outputs are then combined in the digital domain to realize a temperature-independent frequency error signal. This digitally assisted temperature compensation scheme achieves an inaccuracy of ±200 ppm from -45 °C to 85 °C after a two-point trim. The frequency reference draws 430 µA from a 1.8-V supply, while achieving a supply sensitivity of 0.18%/V and a 330-ppb Allan deviation floor in 3 s of measurement time.

  @ARTICLE{mine:jssc2018_cagri,
  author={Ç. {Gürleyük} and L. Pedal\'{a} and S. {Pan} and F. {Sebastiano} and K. A. A. {Makinwa}},
  journal={IEEE Journal of Solid-State Circuits},
  title={A CMOS Dual-RC Frequency Reference With ±200-ppm Inaccuracy From -45 °C to 85 °C},
  year={2018},
  volume={53},
  number={12},
  pages={3386-3395},
  abstract={This paper
  presents a 7-MHz CMOS RC frequency reference. It consists of a
  frequency-locked loop in which the output frequency of a digitally
  controlled oscillator (DCO) is locked to the combined phase shifts
  of two independent RC (Wien bridge) filters, each employing
  resistors with complementary temperature coefficients. The filters
  are driven by the DCO's output frequency and the resulting phase
  shifts are digitized by high-resolution phase-to-digital
  converters. Their outputs are then combined in the digital domain
  to realize a temperature-independent frequency error signal. This
  digitally assisted temperature compensation scheme achieves an
  inaccuracy of ±200 ppm from -45 °C to 85 °C after a two-point trim.
  The frequency reference draws 430 µA from a 1.8-V supply, while
  achieving a supply sensitivity of 0.18%/V and a 330-ppb Allan
  deviation floor in 3 s of measurement time.}, keywords={CMOS
  integrated circuits;compensation;oscillators;RC circuits;reference
  circuits;resistors;CMOS dual-RC frequency
  reference;frequency-locked loop;digitally controlled
  oscillator;combined phase shifts;independent RC
  filters;complementary temperature coefficients;high-resolution
  phase-to-digital converters;digital domain;temperature-independent
  frequency error signal;digitally assisted temperature compensation
  scheme;resistors;DCO;Wien bridge filters;CMOS RC frequency
  reference;current 430.0 muA;time 3.0 s;temperature -45.0 degC to
  85.0 degC;voltage 1.8 V;frequency 7
  MHz;Oscillators;Resistors;Time-frequency analysis;Frequency
  control;Frequency conversion;CMOS;digital frequency-locked loop
  (FLL);digitally controlled oscillator (DCO);integrated frequency
  reference;RC-based},
  doi={10.1109/JSSC.2018.2869083},
  ISSN={0018-9200},
  month={Dec},}

• H. Homulle, F. Sebastiano, and E. Charbon, "Deep-Cryogenic Voltage References in 40-nm CMOS," IEEE Solid-State Circuits Letters, vol. 1, iss. 5, pp. 110-113, 2018.
  [Abstract] [Bibtex]
  

  The increasing interest in electronics specifically designed to control quantum processors is currently driven by the quest for largescale quantum computing. A promising approach is emerging based on the use of CMOS devices operating at deep-cryogenic temperatures, and several essential components have been demonstrated to operate at such temperatures, from basic MOSFETs to field-programmable gate arrays. In this letter, we show, for the first time, a voltage reference in a standard CMOS technology that can guarantee a stable voltage over a wide range of temperatures from 300 K down to deep-cryogenic temperatures. By exploiting CMOS transistors in dynamic-threshold MOS configuration, the proposed reference occupies only 445 µm2 in a standard 40-nm CMOS process, while showing a temperature coefficient below 0.8 mV/K over the temperature range from 4 to 300 K. These results demonstrate the feasibility of wide-range cryogenic voltage references to enable future cryogenic applications.

  @ARTICLE{mine:sscl2019_bandgap,
  author={H. {Homulle} and F. {Sebastiano} and E. {Charbon}},
  journal={IEEE Solid-State Circuits Letters},
  title={Deep-Cryogenic Voltage References in 40-nm CMOS},
  year={2018},
  volume={1},
  number={5},
  pages={110-113},
  abstract={The increasing interest in electronics specifically designed to control quantum processors is currently driven by the quest for largescale quantum computing. A promising approach is emerging based on the use of CMOS devices operating at deep-cryogenic temperatures, and several essential components have been demonstrated to operate at such temperatures, from basic MOSFETs to field-programmable gate arrays. In this letter, we show, for the first time, a voltage reference in a standard CMOS technology that can guarantee a stable voltage over a wide range of temperatures from 300 K down to deep-cryogenic temperatures. By exploiting CMOS transistors in dynamic-threshold MOS configuration, the proposed reference occupies only 445 µm2 in a standard 40-nm CMOS process, while showing a temperature coefficient below 0.8 mV/K over the temperature range from 4 to 300 K. These results demonstrate the feasibility of wide-range cryogenic voltage references to enable future cryogenic applications.},
  keywords={CMOS integrated circuits;cryogenics;field programmable gate arrays;MOSFET circuits;quantum computing;reference circuits;field-programmable gate arrays;voltage reference;standard CMOS technology;deep-cryogenic temperatures;CMOS transistors;CMOS process;deep-cryogenic voltage references;quantum processors;largescale quantum computing;CMOS devices;cryogenic applications;dynamic-threshold MOS configuration;temperature 4.0 K to 300.0 K;size 40 nm;Temperature distribution;Photonic band gap;Cryogenics;CMOS technology;Transistors;Quantum computing;Bandgap;cryogenic;MOS;voltage reference},
  doi={10.1109/LSSC.2018.2875821},
  ISSN={2573-9603},
  month={May},}

2017

• E. Charbon, F. Sebastiano, M. Babaie, A. Vladimirescu, M. Shahmohammadi, R. B. Staszewski, H. A. R. Homulle, B. Patra, J. P. G. van Dijk, R. M. Incandela, L. Song, and B. Valizadehpasha, "Cryo-CMOS circuits and systems for scalable quantum computing," in 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, pp. 264-265.
  [Abstract] [Bibtex]
  

  In Paper 15.5, Delft University of Technology, EPFL, and Intel present building blocks for a scalable CMOS interface to solid-state quantum processors with a projected efficiency of 200µW/qubit. The circuits include an analog noise-canceled 1.2GHz LNA with 28dB gain, a 6.2GHz class-F local oscillator with better than –145dBc/Hz phase noise at 10MHz offset, a 12µm SPAD with 0.1Hz dark count rate at 2V excess bias, and digital logic, all designed using ad hoc deep-cryogenic models.

  @INPROCEEDINGS{mine:isscc_2017_cryoCMOS,
  author={Edoardo Charbon and Fabio Sebastiano and Masoud Babaie and Andrei Vladimirescu and Mina Shahmohammadi and R. B. Staszewski and Harald A. R. Homulle and Bishnu Patra and Jeroen P. G. van Dijk and Rosario M. Incandela and Lin Song and Bahador Valizadehpasha},
  booktitle={2017 IEEE International Solid-State Circuits Conference (ISSCC)},
  title={Cryo-CMOS circuits and systems for scalable quantum computing},
  year={2017},
  pages={264-265},
  abstract={In Paper 15.5, Delft University of Technology, EPFL, and Intel present building blocks for a scalable CMOS interface to solid-state quantum processors with a projected efficiency of 200µW/qubit. The circuits include an
  analog noise-canceled 1.2GHz LNA with 28dB gain, a 6.2GHz class-F local oscillator with better than –145dBc/Hz phase noise at 10MHz offset, a 12µm SPAD with 0.1Hz dark count rate at 2V excess bias, and digital logic, all designed using ad hoc deep-cryogenic models.},
  keywords={CMOS integrated circuits;logic circuits;quantum computing;cryo-CMOS circuits;error-correcting loop;quantum algorithm;quantum bits arrays;quantum coherence loss;qubit states;room-temperature controller;scalable quantum computing;state-of-the-art quantum processors;unprecedented computation power;Cryogenics;Oscillators;Program processors;Quantum computing;Semiconductor
  device modeling;Substrates;Temperature sensors},
  doi={10.1109/ISSCC.2017.7870362},
  month={Feb},}

• B. Gönen, F. Sebastiano, and R. V. K. H. M. A. A. van Makinwa, "A hybrid ADC for high resolution: the Zoom ADC," in Proc. Workshop on Advances in Analog Circuit Design (AACD), Eindhoven, The Netherlands, 2017.
  [Bibtex]

  @INPROCEEDINGS{mine:aacd_2017,
  author={Burak Gönen and Fabio Sebastiano and Robert H. M. van Veldhoven Kofi A. A. Makinwa},
  booktitle={Proc. Workshop on Advances in Analog Circuit Design (AACD)},
  title="A hybrid {ADC} for high resolution: the Zoom {ADC}",
  year={2017},
  pages={},
  address={Eindhoven, The Netherlands},
  abstract={},
  keywords={},
  doi={10.1109/IWASI.2017.7974215},
  month=Mar,}

• F. Sebastiano, H. A. R. Homulle, J. P. G. van Dijk, R. M. Incandela, B. Patra, M. Mehrpoo, M. Babaie, A. Vladimirescu, and E. Charbon, "Cryogenic CMOS interfaces for quantum devices," in 2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI), Vieste, Italy, 2017, pp. 59-62.
  [Abstract] [Bibtex]
  

  Quantum computers could efficiently solve problems that are intractable by today's computers, thus offering the possibility to radically change entire industries and revolutionize our lives. A quantum computer comprises a quantum processor operating at cryogenic temperature and an electronic interface for its control, which is currently implemented at room temperature for the few qubits available today. However, this approach becomes impractical as the number of qubits grows towards the tens of thousands required for complex quantum algorithms with practical applications. We propose an electronic interface for sensing and controlling qubits operating at cryogenic temperature implemented in standard CMOS.

  @INPROCEEDINGS{mine:iwasi_2017,
  author={Fabio Sebastiano and Harald A. R. Homulle and Jeroen P. G. van Dijk and Rosario M. Incandela and Bishnu Patra and M. Mehrpoo and Masoud Babaie and Andrei Vladimirescu and Edoardo Charbon},
  booktitle={2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI)},
  title={Cryogenic CMOS interfaces for quantum devices},
  year={2017},
  address={Vieste, Italy},
  pages={59-62},
  abstract={Quantum computers could efficiently solve problems that are intractable by today's computers, thus offering the possibility to radically change entire industries and revolutionize our lives. A quantum computer comprises a quantum processor operating at cryogenic temperature and an electronic interface for its control, which is currently implemented at room temperature for the few qubits available today. However, this approach becomes impractical as the number of qubits grows towards the tens of thousands required for complex quantum algorithms with practical applications. We propose an electronic interface for sensing and controlling qubits operating at cryogenic temperature implemented in standard CMOS.},
  keywords={CMOS technology;Computers;Cryogenics;Process control;Quantum computing;Semiconductor device modeling;Standards;CMOS;cryo-CMOS;cryogenics;quantum computing;qubits},
  doi={10.1109/IWASI.2017.7974215},
  month={June},}

• F. Sebastiano, H. Homulle, B. Patra, R. Incandela, J. van Dijk, L. Song, M. Babaie, A. Vladimirescu, and E. Charbon, "Cryo-CMOS Electronic Control for Scalable Quantum Computing: Invited," in Proceedings of the 54th Annual Design Automation Conference 2017, New York, NY, USA, 2017, p. 13:1--13:6.
  [Bibtex]

  @inproceedings{mine:dac_2017,
  author = {Fabio Sebastiano and Harald Homulle and Bishnu Patra and Rosario Incandela and Jeroen van Dijk and Lin Song and Masoud Babaie and Andrei Vladimirescu and Edoardo Charbon},
  title = {Cryo-CMOS Electronic Control for Scalable Quantum Computing: Invited},
  booktitle = {Proceedings of the 54th Annual Design Automation Conference 2017},
  series = {DAC '17},
  year = {2017},
  isbn = {978-1-4503-4927-7},
  location = {Austin, TX, USA},
  pages = {13:1--13:6},
  articleno = {13},
  numpages = {6},
  url = {http://doi.acm.org/10.1145/3061639.3072948},
  doi = {10.1145/3061639.3072948},
  acmid = {3072948},
  publisher = {ACM},
  address = {New York, NY, USA},
  keywords = {Cryo-CMOS, cryogenics, device models, error-correcting loop, quantum computation, qubit},
  }

• L. Pedalà, &. Gürleyük, S. Pan, F. Sebastiano, and K. A. A. Makinwa, "A Frequency-Locked Loop Based on an Oxide Electrothermal Filter in Standard CMOS," in Proc. European Solid-State Circuits Conference, Leuven, Belgium, 2017, pp. 7-10.
  [Abstract] [Bibtex]
  

  The thermal diffusivity of silicon DSi has been used to realize fully-CMOS frequency references. However, due to the temperature dependence of Dg, the accuracy of such frequency references is limited to about 1000 ppm (-55 °C to 125 °C, one-point trim) due to the inaccuracy of the on-chip temperature compensation circuitry. As an alternative, we propose a frequency reference based on the thermal diffusivity of silicon dioxide Dox. Since the temperature dependence of Dqx is much less than that of Dg, the resulting frequency reference will be much more stable over temperature. To investigate this idea, a thermal-diffusivity-based frequency-locked loop (FLL) was realized in 0.18-µm CMOS. With ideal temperature compensation, the proposed frequency reference achieves an inaccuracy of 90 ppm (-45 °C to 85 °C, two-point trim). Even with 0.1 °C inaccuracy, which can be achieved by BJT-based temperature sensors, 200 ppm can still be achieved. This demonstrates the feasibility of high-accuracy oxide-based frequency references in standard CMOS.

  @INPROCEEDINGS{mine:esscirc_2017_lorenzo,
  author = {Lorenzo Pedalà and Çagri Gürleyük and Sining Pan and Fabio Sebastiano and Kofi A.A. Makinwa},
  booktitle="Proc. {European Solid-State Circuits Conference}",
  title="A Frequency-Locked Loop Based on an Oxide Electrothermal Filter in Standard {CMOS}",
  year={2017},
  month=sep,
  address={Leuven, Belgium},
  pages={7-10},
  abstract={The thermal diffusivity of silicon DSi has been used to realize fully-CMOS frequency references. However, due to the temperature dependence of Dg, the accuracy of such frequency references is limited to about 1000 ppm (-55 °C to 125 °C, one-point trim) due to the inaccuracy of the on-chip temperature compensation circuitry. As an alternative, we propose a frequency reference based on the thermal diffusivity of silicon dioxide Dox. Since the temperature dependence of Dqx is much less than that of Dg, the resulting frequency reference will be much more stable over temperature. To investigate this idea, a thermal-diffusivity-based frequency-locked loop (FLL) was realized in 0.18-µm CMOS. With ideal temperature compensation, the proposed frequency reference achieves an inaccuracy of 90 ppm (-45 °C to 85 °C, two-point trim). Even with 0.1 °C inaccuracy, which can be achieved by BJT-based temperature sensors, 200 ppm can still be achieved. This demonstrates the feasibility of high-accuracy oxide-based frequency references in standard CMOS.},
  keywords={CMOS integrated circuits;bipolar transistors;compensation;filters;frequency locked loops;temperature measurement;temperature sensors;thermal conductivity measurement;thermal diffusivity;BJT-based temperature sensors;FLL;frequency-locked loop;fully-CMOS frequency references;high-accuracy oxide-based frequency references;on-chip temperature compensation circuitry;oxide electrothermal filter;size 0.18 mum;temperature -45.0 degC to 85.0 degC;temperature -55.0 degC to 125.0 degC;temperature 0.1 degC;thermal diffusivity;Frequency locked loops;Heating systems;Resistors;Silicon;Temperature dependence;Temperature measurement;Temperature sensors;CMOS;frequency reference;oxide;thermal diffusivity},
  doi={10.1109/ESSCIRC.2017.8094512},
  ISSN={}
  }

• R. M. Incandela, L. Song, H. Homulle, F. Sebastiano, E. Charbon, and A. Vladimirescu, "Nanometer CMOS Characterization and Compact Modeling at Deep-Cryogenic Temperatures," in Proc. European European Solid-State Device Research Conference, Leuven, Belgium, 2017, pp. 395-398.
  [Abstract] [Bibtex]
  

  The characterization of nanometer CMOS transistors of different aspect ratios at deep-cryogenic temperatures (4 K and 100 mK) is presented for two standard CMOS technologies (40 nm and 160 nm). A detailed understanding of the device physics at those temperatures was developed and captured in an augmented MOS11/PSP model. The accuracy of the proposed model is demonstrated by matching simulations and measurements for DC and time-domain at 4 K and, for the first time, at 100 mK.

  @INPROCEEDINGS{mine:essderc_2017_rosario,
  author = {Rosario M. Incandela and Lin Song and Harald Homulle and Fabio Sebastiano and Edoardo Charbon and Andrei Vladimirescu},
  booktitle="Proc. {European European Solid-State Device Research Conference}",
  title="Nanometer {CMOS} Characterization and Compact Modeling at Deep-Cryogenic Temperatures",
  year={2017},
  month=sep ,
  address="Leuven, Belgium",
  pages={395-398},
  abstract={The characterization of nanometer CMOS transistors of different aspect ratios at deep-cryogenic temperatures (4 K and 100 mK) is presented for two standard CMOS technologies (40 nm and 160 nm). A detailed understanding of the device physics at those temperatures was developed and captured in an augmented MOS11/PSP model. The accuracy of the proposed model is demonstrated by matching simulations and measurements for DC and time-domain at 4 K and, for the first time, at 100 mK.},
  keywords={CMOS integrated circuits;system-on-chip;temperature measurement;temperature sensors;thermal diffusivity;SoC thermal monitoring;area-optimized thermal-diffusivity-based temperature sensor;bulk silicon;microprocessors;size 160 nm;standard CMOS process;systems-on-chip;temperature-dependent thermal diffusivity;thermal monitoring;Accuracy;Heating;System-on-chip;Temperature measurement;Temperature sensors},
  doi={10.1109/ESSCIRC.2014.6942105},
  ISSN={1930-8833}
  }

• E. Prati, D. Rotta, F. Sebastiano, and E. Charbon, "From the Quantum Moore's Law toward Silicon Based Universal Quantum Computing," in 2017 IEEE International Conference on Rebooting Computing (ICRC), 2017, pp. 1-4.
  [Bibtex]

  @INPROCEEDINGS{mine:icrc2017,
  author={Enrico Prati and Davide Rotta and Fabio Sebastiano and Edoardo Charbon},
  booktitle={2017 IEEE International Conference on Rebooting Computing (ICRC)},
  title={From the Quantum Moore's Law toward Silicon Based Universal Quantum Computing},
  year={2017},
  volume={},
  number={},
  pages={1-4},
  keywords={CMOS logic circuits;concatenated codes;error correction;quantum entanglement;quantum gates;CMOS single donors;CMOS technology nodes;Steane code;concatenated codes;density scaling;double quantum dot devices;intrinsic operation speed limitation;physical silicon qubit;principle support error-free logical qubits;quantum Moore law;quantum computer;quantum error correction architectures;quantum information density;quantum information equivalent;quantum logic gates;quantum technology platforms;scaling law;silicon based universal quantum computing;silicon qubit architectures;silicon technology;standard CMOS design rules;surface code;universal set;CMOS technology;Computer architecture;Logic gates;Market research;Quantum computing;Quantum dots;Silicon},
  doi={10.1109/ICRC.2017.8123662},
  ISSN={},
  month={Nov},}

• B. Gönen, F. Sebastiano, R. Quan, R. van Veldhoven, and K. A. A. Makinwa, "A Dynamic Zoom ADC With 109-dB DR for Audio Applications," IEEE Journal of Solid-State Circuits, vol. 52, iss. 6, pp. 1542-1550, 2017.
  [Abstract] [Bibtex]
  

  This paper presents the first dynamic zoom ADC. Intended for audio applications, it achieves 109-dB DR, 106-dB signal-to-noise ratio, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating only 1.12 mW. This translates into the state-of-the-art energy efficiency as expressed by a Schreier FoM of 181.5 dB. It also achieves the state-of-the-art area efficiency, occupying only 0.16 mm² in the 0.16-µm CMOS. These advances are enabled by the use of concurrent fine and coarse conversions, dynamic error-correction techniques, and a dynamically biased inverter-based operational transconductance amplifier.

  @ARTICLE{mine:jssc_2017_burak,
  author={Burak Gönen and Fabio Sebastiano and Rui Quan and Robert van Veldhoven and Kofi A.A. Makinwa},
  journal={IEEE Journal of Solid-State Circuits},
  title={A Dynamic Zoom ADC With 109-dB DR for Audio Applications},
  year={2017},
  volume={52},
  number={6},
  pages={1542-1550},
  abstract={This paper presents the first dynamic zoom ADC. Intended for audio applications, it achieves 109-dB DR, 106-dB signal-to-noise ratio, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating only 1.12 mW. This translates into the state-of-the-art energy efficiency as expressed by a Schreier FoM of 181.5 dB. It also achieves the state-of-the-art area efficiency, occupying only 0.16 mm² in the 0.16-µm CMOS. These advances are enabled by the use of concurrent fine and coarse conversions, dynamic error-correction techniques, and a dynamically biased inverter-based operational transconductance amplifier.},
  keywords={CMOS integrated circuits;analogue-digital conversion;audio signal processing;error correction;invertors;operational amplifiers;CMOS;Schreier FoM;area efficiency;audio applications;bandwidth 20 kHz;coarse conversions;concurrent fine conversions;dynamic error-correction techniques;dynamic zoom ADC;dynamically biased inverter;energy efficiency;operational transconductance amplifier;power 1.12 mW;signal-to-noiseratio;size 0.16 mum;Bandwidth;Dynamic range;Linearity;Quantization (signal);Signal resolution;Signal to noise ratio;Vehicle dynamics;Audio;compact ADC;delta sigma;discrete time;dynamic;dynamic range (DR);hybrid ADC;precision;zoom ADC},
  doi={10.1109/JSSC.2017.2669022},
  ISSN={0018-9200},
  month={June}
  }

• U. Sönmez, F. Sebastiano, and K. A. A. Makinwa, "Compact Thermal-Diffusivity-Based Temperature Sensors in 40-nm CMOS for SoC Thermal Monitoring," IEEE Journal of Solid-State Circuits, vol. 52, iss. 3, pp. 834-843, 2017.
  [Abstract] [Bibtex]
  

  An array of temperature sensors based on the thermal diffusivity (TD) of bulk silicon has been realized in a standard 40-nm CMOS process. In each TD sensor, a highly digital voltage-controlled oscillator-based S? ADC digitizes the temperature-dependent phase shift of an electrothermal filter (ETF). A phase calibration scheme is used to cancel the ADC's phase offset. Two types of ETF were realized, one optimized for accuracy and one optimized for resolution. Sensors based on the accuracy-optimized ETF achieved a resolution of 0.36 °C (rms) at 1 kSa/s, and inaccuracies of ±1.4 °C (3σ, uncalibrated) and ±0.75 °C (3s, room-temperature calibrated) from -40 °C to 125 °C. Sensors based on the resolution-optimized ETFs achieved an improved resolution of 0.21 °C (rms), and inaccuracies of ±2.3 °C (3σ, uncalibrated) and ±1.05 °C (3σ, room-temperature calibrated). The sensors draw 2.8 mA from supply voltages as low as 0.9 V, and occupy only 1650 µm2, making them some of the smallest smart temperature sensors reported to date, and well suited for thermal monitoring applications in systems-on-chip.

  @ARTICLE{mine:jssc_ugur_2017,
  author={Ugur Sönmez and Fabio Sebastiano and Kofi A. A. Makinwa},
  journal={IEEE Journal of Solid-State Circuits},
  title={Compact Thermal-Diffusivity-Based Temperature Sensors in 40-nm CMOS for SoC Thermal Monitoring},
  year={2017},
  volume={52},
  number={3},
  pages={834-843},
  abstract={An array of temperature sensors based on the thermal diffusivity (TD) of bulk silicon has been realized in a standard 40-nm CMOS process. In each TD sensor, a highly digital voltage-controlled oscillator-based S? ADC digitizes the temperature-dependent phase shift of an electrothermal filter (ETF). A phase calibration scheme is used to cancel the ADC's phase offset. Two types of ETF were realized, one optimized for accuracy and one optimized for resolution. Sensors based on the accuracy-optimized ETF achieved a resolution of 0.36 °C (rms) at 1 kSa/s, and inaccuracies of ±1.4 °C (3σ, uncalibrated) and ±0.75 °C (3s, room-temperature calibrated) from -40 °C to 125 °C. Sensors based on the resolution-optimized ETFs achieved an improved resolution of 0.21 °C (rms), and inaccuracies of ±2.3 °C (3σ, uncalibrated) and ±1.05 °C (3σ, room-temperature calibrated). The sensors draw 2.8 mA from supply voltages as low as 0.9 V, and occupy only 1650 µm2, making them some of the smallest smart temperature sensors reported to date, and well suited for thermal monitoring applications in systems-on-chip.},
  keywords={CMOS integrated circuits;sigma-delta modulation;system-on-chip;temperature sensors;thermal diffusivity;voltage-controlled oscillators;CMOS process;SoC thermal monitoring;accuracy-optimized ETF;bulk silicon;current 2.8 mA;electrothermal filter;phase calibration scheme;resolution-optimized ETF;size 40 nm;smart temperature sensors;systems-on-chip;temperature -40 C to 125 C;temperature-dependent phase shift;thermal diffusivity;voltage 0.9 V;voltage-controlled oscillator-based S? ADC;Calibration;Heating;Intelligent sensors;Temperature sensors;Voltage-controlled oscillators;Phase-to-digital converter;temperature sensors;thermal diffusivity (TD);thermal monitoring;voltage-controlled oscillator (VCO)-based sigma–delta modulator},
  doi={10.1109/JSSC.2016.2646798},
  ISSN={0018-9200},
  month={Mar}}

• U. Sönmez, F. Sebastiano, and K. A. A. Makinwa, "Analysis and Design of VCO-Based Phase-Domain $\Sigma \Delta $ Modulators," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, iss. 5, pp. 1075-1084, 2017.
  [Abstract] [Bibtex]
  

  VCO-based phase-domain $\Sigma\Delta$ modulators employ the combination of a voltage-controlled-oscillator (VCO) and an up/down counter to replace the analog loop filter used in conventional $\Sigma\Delta$ modulators. Thanks to this highly digital architecture, they can be quite compact, and are expected to shrink even further with CMOS scaling. This paper describes the analysis and design of such converters. Trade-offs between design parameters and the impact of non-idealities, such as finite counter length and VCO non-linearity, are assessed through both theoretical analysis and behavioral simulations. The proposed design methodology is applied to the design of a phase-to-digital converter in a 40-nm CMOS process, which is used to digitize the output of a thermal-diffusivity temperature sensor, achieving ± 0.2° (3σ) phase inaccuracy from -40 to 125 °C and a sensor-limited resolution of 57 m$\Sigma\Delta$ (RMS) within a 500-Hz bandwidth. Measurements on the prototype agree quite well with theoretical predictions, thus demonstrating the validity of the proposed design methodology.

  @ARTICLE{mine:tcas_ugur_2017,
  author={Ugur Sönmez and Fabio Sebastiano and Kofi A. A. Makinwa},
  journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
  title={Analysis and Design of VCO-Based Phase-Domain $\Sigma \Delta $
  Modulators},
  year={2017},
  volume={64},
  number={5},
  pages={1075-1084},
  abstract={VCO-based phase-domain $\Sigma\Delta$ modulators employ the combination of a voltage-controlled-oscillator (VCO) and an up/down counter to replace the analog loop filter used in conventional $\Sigma\Delta$ modulators. Thanks to this highly digital architecture, they can be quite compact, and are expected to shrink even further with CMOS scaling. This paper describes the analysis and design of such converters. Trade-offs between design parameters and the impact of non-idealities, such as finite counter length and VCO non-linearity, are assessed through both theoretical analysis and behavioral simulations. The proposed design methodology is applied to the design of a phase-to-digital converter in a 40-nm CMOS process, which is used to digitize the output of a thermal-diffusivity temperature sensor, achieving ± 0.2° (3σ) phase inaccuracy from -40 to 125 °C and a sensor-limited resolution of 57 m$\Sigma\Delta$ (RMS) within a 500-Hz bandwidth. Measurements on the prototype agree quite well with theoretical predictions, thus demonstrating the validity of the proposed design methodology.},
  keywords={CMOS digital integrated circuits;sigma-delta modulation;voltage-controlled oscillators;CMOS process;CMOS scaling;VCO nonlinearity;VCO-based phase-domain S? modulators;analog loop filter;bandwidth 500 Hz;finite counter length;phase-to-digital converter;size 40 nm;temperature -40 C to 125 C;thermal-diffusivity temperature sensor;up-down counter;voltage-controlled-oscillator;Phase modulation;Quantization (signal);Radiation detectors;Temperature sensors;Voltage-controlled oscillators;Phase-to-digital converter;VCO-based sigma-delta modulator;quantization noise;time-to-digital converter},
  doi={10.1109/TCSI.2016.2638827},
  ISSN={1549-8328},
  month={May},}

• D. Rotta, F. Sebastiano, E. Charbon, and E. Prati, "Quantum information density scaling and qubit operation time constraints of CMOS silicon-based quantum computer architectures," npj Quantum Information, vol. 3, iss. 1, p. 26, 2017.
  [Abstract] [Bibtex]
  

  Even the quantum simulation of an apparently simple molecule such as Fe2S2 requires a considerable number of qubits of the order of 106, while more complex molecules such as alanine (C3H7NO2) require about a hundred times more. In order to assess such a multimillion scale of identical qubits and control lines, the silicon platform seems to be one of the most indicated routes as it naturally provides, together with qubit functionalities, the capability of nanometric, serial, and industrial-quality fabrication. The scaling trend of microelectronic devices predicting that computing power would double every 2 years, known as Moore’s law, according to the new slope set after the 32-nm node of 2009, suggests that the technology roadmap will achieve the 3-nm manufacturability limit proposed by Kelly around 2020. Today, circuital quantum information processing architectures are predicted to take advantage from the scalability ensured by silicon technology. However, the maximum amount of quantum information per unit surface that can be stored in silicon-based qubits and the consequent space constraints on qubit operations have never been addressed so far. This represents one of the key parameters toward the implementation of quantum error correction for fault-tolerant quantum information processing and its dependence on the features of the technology node. The maximum quantum information per unit surface virtually storable and controllable in the compact exchange-only silicon double quantum dot qubit architecture is expressed as a function of the complementary metal–oxide–semiconductor technology node, so the size scale optimizing both physical qubit operation time and quantum error correction requirements is assessed by reviewing the physical and technological constraints. According to the requirements imposed by the quantum error correction method and the constraints given by the typical strength of the exchange coupling, we determine the workable operation frequency range of a silicon complementary metal–oxide–semiconductor quantum processor to be within 1 and 100?GHz. Such constraint limits the feasibility of fault-tolerant quantum information processing with complementary metal–oxide–semiconductor technology only to the most advanced nodes. The compatibility with classical complementary metal–oxide–semiconductor control circuitry is discussed, focusing on the cryogenic complementary metal–oxide–semiconductor operation required to bring the classical controller as close as possible to the quantum processor and to enable interfacing thousands of qubits on the same chip via time-division, frequency-division, and space-division multiplexing. The operation time range prospected for cryogenic control electronics is found to be compatible with the operation time expected for qubits. By combining the forecast of the development of scaled technology nodes with operation time and classical circuitry constraints, we derive a maximum quantum information density for logical qubits of 2.8 and 4?Mqb/cm2 for the 10 and 7-nm technology nodes, respectively, for the Steane code. The density is one and two orders of magnitude less for surface codes and for concatenated codes, respectively. Such values provide a benchmark for the development of fault-tolerant quantum algorithms by circuital quantum information based on silicon platforms and a guideline for other technologies in general.

  @Article{mine:npj_quantum_information_2017,
  author={Davide Rotta and Fabio Sebastiano and Edoardo Charbon and Enrico Prati},
  title={Quantum information density scaling and qubit operation time constraints of CMOS silicon-based quantum computer architectures},
  journal={npj Quantum Information},
  year={2017},
  volume={3},
  number={1},
  pages={26},
  issn={2056-6387},
  doi={10.1038/s41534-017-0023-5},
  abstract={Even the quantum simulation of an apparently simple molecule such as Fe2S2 requires a considerable number of qubits of the order of 106, while more complex molecules such as alanine (C3H7NO2) require about a hundred times more. In order to assess such a multimillion scale of identical qubits and control lines, the silicon platform seems to be one of the most indicated routes as it naturally provides, together with qubit functionalities, the capability of nanometric, serial, and industrial-quality fabrication. The scaling trend of microelectronic devices predicting that computing power would double every 2 years, known as Moore’s law, according to the new slope set after the 32-nm node of 2009, suggests that the technology roadmap will achieve the 3-nm manufacturability limit proposed by Kelly around 2020. Today, circuital quantum information processing architectures are predicted to take advantage from the scalability ensured by silicon technology. However, the maximum amount of quantum information per unit surface that can be stored in silicon-based qubits and the consequent space constraints on qubit operations have never been addressed so far. This represents one of the key parameters toward the implementation of quantum error correction for fault-tolerant quantum information processing and its dependence on the features of the technology node. The maximum quantum information per unit surface virtually storable and controllable in the compact exchange-only silicon double quantum dot qubit architecture is expressed as a function of the complementary metal–oxide–semiconductor technology node, so the size scale optimizing both physical qubit operation time and quantum error correction requirements is assessed by reviewing the physical and technological constraints. According to the requirements imposed by the quantum error correction method and the constraints given by the typical strength of the exchange coupling, we determine the workable operation frequency range of a silicon complementary metal–oxide–semiconductor quantum processor to be within 1 and 100?GHz. Such constraint limits the feasibility of fault-tolerant quantum information processing with complementary metal–oxide–semiconductor technology only to the most advanced nodes. The compatibility with classical complementary metal–oxide–semiconductor control circuitry is discussed, focusing on the cryogenic complementary metal–oxide–semiconductor operation required to bring the classical controller as close as possible to the quantum processor and to enable interfacing thousands of qubits on the same chip via time-division, frequency-division, and space-division multiplexing. The operation time range prospected for cryogenic control electronics is found to be compatible with the operation time expected for qubits. By combining the forecast of the development of scaled technology nodes with operation time and classical circuitry constraints, we derive a maximum quantum information density for logical qubits of 2.8 and 4?Mqb/cm2 for the 10 and 7-nm technology nodes, respectively, for the Steane code. The density is one and two orders of magnitude less for surface codes and for concatenated codes, respectively. Such values provide a benchmark for the development of fault-tolerant quantum algorithms by circuital quantum information based on silicon platforms and a guideline for other technologies in general.},
  url={https://doi.org/10.1038/s41534-017-0023-5}
  }

• H. Homulle, S. Visser, B. Patra, G. Ferrari, E. Prati, F. Sebastiano, E. Charbon, and E. Prati, "A reconfigurable cryogenic platform for the classical control of quantum processors," Review of Scientific Instruments, vol. 88, iss. 4, p. 45103, 2017.
  [Abstract] [Bibtex]
  

  The implementation of a classical control infrastructure for large-scale quantum computers is challenging due to the need for integration and processing time, which is constrained by coherence time. We propose a cryogenic reconfigurable platform as the heart of the control infrastructure implementing the digital error-correction control loop. The platform is implemented on a field-programmable gate array (FPGA) that supports the functionality required by several qubit technologies and that can operate close to the physical qubits over a temperature range from 4 K to 300 K. This work focuses on the extensive characterization of the electronic platform over this temperature range. All major FPGA building blocks (such as look-up tables (LUTs), carry chains (CARRY4), mixed-mode clock manager (MMCM), phase-locked loop (PLL), block random access memory, and IDELAY2 (programmable delay element)) operate correctly and the logic speed is very stable. The logic speed of LUTs and CARRY4 changes less then 5%, whereas the jitter of MMCM and PLL clock managers is reduced by 20%. The stability is finally demonstrated by operating an integrated 1.2 GSa/s analog-to-digital converter (ADC) with a relatively stable performance over temperature. The ADCs effective number of bits drops from 6 to 4.5 bits when operating at 15 K.

  @Article{mine:rsi_2017,
  author={Harald Homulle and Stefan Visser and Bishnu Patra and Giorgio Ferrari and Enrico Prati and Fabio Sebastiano and Edoardo Charbon and Enrico Prati},
  title={A reconfigurable cryogenic platform for the classical control of quantum processors},
  journal={Review of Scientific Instruments},
  year={2017},
  volume={88},
  number={4},
  pages={045103},
  doi={10.1063/1.4979611},
  abstract={The implementation of a classical control infrastructure for large-scale quantum computers is challenging due to the need for integration and processing time, which is constrained by coherence time. We propose a cryogenic reconfigurable platform as the heart of the control infrastructure implementing the digital error-correction control loop. The platform is implemented on a field-programmable gate array (FPGA) that supports the functionality required by several qubit technologies and that can operate close to the physical qubits over a temperature range from 4 K to 300 K. This work focuses on the extensive characterization of the electronic platform over this temperature range. All major FPGA building blocks (such as look-up tables (LUTs), carry chains (CARRY4), mixed-mode clock manager (MMCM), phase-locked loop (PLL), block random access memory, and IDELAY2 (programmable delay element)) operate correctly and the logic speed is very stable. The logic speed of LUTs and CARRY4 changes less then 5%, whereas the jitter of MMCM and PLL clock managers is reduced by 20%. The stability is finally demonstrated by operating an integrated 1.2 GSa/s analog-to-digital converter (ADC) with a relatively stable performance over temperature. The ADCs effective number of bits drops from 6 to 4.5 bits when operating at 15 K.},
  url={https://doi.org/10.1063/1.4979611}
  }

2016

• U. Sönmez, F. Sebastiano, and K. A. A. Makinwa, "1650µm² Thermal-Diffusivity Sensors with Inaccuracies Down to ±0.75$^\circ$C in 40nm CMOS," in International Solid-state Circuits Conference Digest of Technical Papers, San Francisco, CA, 2016, pp. 206-207.
  [Abstract] [Bibtex]
  

  This work presents a thermal diffusivity (TD) sensor realized in nanometer (40nm) CMOS that demonstrates that the performance of such sensors continues to improve with scaling. Without trimming, the sensor achieves ±1.4°C (3s) inaccuracy from -40 to 125°C, which is a 5× improvement over previous (non-TD) sensors intended for thermal monitoring. This improves to ±0.75°C (3s) after a single-point trim, a level of accuracy that previously would have required two-point trimming. Furthermore, it operates from supply voltages as low as 0.9V, and occupies only 1650 µm2, making it one of the smallest smart temperature sensors reported to date. These advances are enabled by the use of a phase-calibration scheme and a highly digital phase-domain ?S ADC.

  @INPROCEEDINGS{mine:isscc_2016_ugur,
  author={Ugur Sönmez and Fabio Sebastiano and Kofi A.A. Makinwa},
  booktitle={International Solid-state Circuits Conference Digest of Technical Papers},
  address="San Francisco, CA",
  title="1650µm² Thermal-Diffusivity Sensors with Inaccuracies Down to ±0.75$^\circ$C in 40nm {CMOS}",
  year={2016},
  pages={206-207},
  abstract={This work presents a thermal diffusivity (TD) sensor realized in nanometer (40nm) CMOS that demonstrates that the performance of such sensors continues to improve with scaling. Without trimming, the sensor achieves ±1.4°C (3s) inaccuracy from -40 to 125°C, which is a 5× improvement over previous (non-TD) sensors intended for thermal monitoring. This improves to ±0.75°C (3s) after a single-point trim, a level of accuracy that previously would have required two-point trimming. Furthermore, it operates from supply voltages as low as 0.9V, and occupies only 1650 µm2, making it one of the smallest smart temperature sensors reported to date. These advances are enabled by the use of a phase-calibration scheme and a highly digital phase-domain ?S ADC.},
  keywords={CMOS integrated circuits;calibration;delta-sigma modulation;temperature sensors;thermal diffusivity;CMOS;digital phase-domain ?S ADC;phase-calibration scheme;scaling;single-point trim;size 40 nm;smart temperature sensors;temperature -40 degC to 125 degC;thermal monitoring;thermal-diffusivity sensors;CMOS integrated circuits;Monitoring;Radiation detectors;Temperature measurement;Temperature sensors},
  doi={10.1109/ISSCC.2016.7417979},
  month={Jan}}

• B. Gönen, F. Sebastiano, R. and Veldhoven, and K. A. A. Makinwa, "A 1.65mW 0.16mm² Dynamic Zoom-ADC with 107.5dB DR in 20kHz BW," in International Solid-state Circuits Conference Digest of Technical Papers, San Francisco, CA, 2016, pp. 282-283.
  [Abstract] [Bibtex]
  

  Audio codecs for automotive applications and smartphones require up to five stereo channels to achieve effective acoustic noise and echo cancellation, thus demanding ADCs with low power and minimal die area. Zoom-ADCs should be well suited for such applications, since they combine compact and energy-efficient SAR ADCs with low-distortion ?S ADCs to simultaneously achieve high energy efficiency, small die area, and high linearity [1,2]. However, previous implementations were limited to the conversion of quasi-static signals, since the two ADCs were operated sequentially, with a coarse SAR conversion followed by, a much slower, fine ?S conversion. This work describes a zoom-ADC with a 20kHz bandwidth, which achieves 107.5dB DR and 104.4dB SNR while dissipating 1.65mW and occupying 0.16mm2. A comparison with recent state-of-the-art ADCs with similar resolution and bandwidth [3-7] shows that the ADC achieves significantly improved energy and area efficiency. These advances are enabled by the use of concurrent fine and coarse conversions, dynamic error-correction techniques, and an inverter-based OTA.

  @INPROCEEDINGS{mine:isscc_2016_burak,
  author={Burak Gönen and Fabio Sebastiano and and Robert.van Veldhoven and Kofi A.A. Makinwa},
  booktitle={International Solid-state Circuits Conference Digest of Technical Papers},
  address="San Francisco, CA",
  title="A 1.65m{W} 0.16mm² Dynamic {Zoom-ADC with 107.5dB DR in 20kHz BW}",
  year={2016},
  pages={282-283},
  abstract={Audio codecs for automotive applications and smartphones require up to five stereo channels to achieve effective acoustic noise and echo cancellation, thus demanding ADCs with low power and minimal die area. Zoom-ADCs should be well suited for such applications, since they combine compact and energy-efficient SAR ADCs with low-distortion ?S ADCs to simultaneously achieve high energy efficiency, small die area, and high linearity [1,2]. However, previous implementations were limited to the conversion of quasi-static signals, since the two ADCs were operated sequentially, with a coarse SAR conversion followed by, a much slower, fine ?S conversion. This work describes a zoom-ADC with a 20kHz bandwidth, which achieves 107.5dB DR and 104.4dB SNR while dissipating 1.65mW and occupying 0.16mm2. A comparison with recent state-of-the-art ADCs with similar resolution and bandwidth [3-7] shows that the ADC achieves significantly improved energy and area efficiency. These advances are enabled by the use of concurrent fine and coarse conversions, dynamic error-correction techniques, and an inverter-based OTA.},
  keywords={codecs;delta-sigma modulation;energy conservation;error correction;invertors;operational amplifiers;SNR;acoustic noise;audio codec;automotive application;bandwidth 20 kHz;dynamic zoom-ADC;echo cancellation;energy-efficient SAR ADC;error-correction technique;inverter-based OTA;low-distortion ?S ADC;operational transconductance amplifier;power 1.65 mW;quasistatic signal;signal-noise ratio;smartphone;stereo channel;successive approximation register analog-digital converter;Bandwidth;Capacitors;Energy efficiency;Linearity;Modulation;Solid state circuits;Vehicle dynamics},
  doi={10.1109/ISSCC.2016.7418017},
  month={Jan}}

• H. Homulle, S. Visser, B. Patra, G. Ferrari, E. Prati, C. G. Almudéver, K. Bertels, F. Sebastiano, and E. Charbon, "CryoCMOS Hardware Technology a Classical Infrastructure for a Scalable Quantum Computer," in Proceedings of the ACM International Conference on Computing Frontiers, New York, NY, USA, 2016, pp. 282-287.
  [Abstract] [Bibtex]
  

  We propose a classical infrastructure for a quantum computer implemented in CMOS. The peculiarity of the approach is to operate the classical CMOS circuits and systems at deep cryogenic temperatures (cryoCMOS), so as to ensure physical proximity to the quantum bits, thus reducing thermal gradients and increasing compactness. CryoCMOS technology leverages the CMOS fabrication infrastructure and exploits the continuous effort of miniaturization that has sustained Moore’s Law for over 50 years. Such approach is believed to enable the growth of the number of qubits operating in a fault-tolerant fashion, paving the way to scalable quantum computing machines.

  @inproceedings{mine:computer_frontiers_2016_homulle,
  author = {Harald Homulle and Stefan Visser and Bishnu Patra and Giorgio Ferrari and Enrico Prati and Carmen G. Almud{\'e}ver and Koen Bertels and Fabio Sebastiano and Edoardo Charbon},
  title = {CryoCMOS Hardware Technology a Classical Infrastructure for a Scalable Quantum Computer},
  booktitle = {Proceedings of the ACM International Conference on Computing Frontiers},
  series = {CF '16},
  year = {2016},
  isbn = {978-1-4503-4128-8},
  location = {Como, Italy},
  pages = {282--287},
  numpages = {6},
  url = {http://doi.acm.org/10.1145/2903150.2906828},
  doi = {10.1145/2903150.2906828},
  acmid = {2906828},
  publisher = {ACM},
  address = {New York, NY, USA},
  abstract={We propose a classical infrastructure for a quantum computer implemented in CMOS. The peculiarity of the approach is to operate the classical CMOS circuits and systems at deep cryogenic temperatures (cryoCMOS), so as to ensure physical proximity to the quantum bits, thus reducing thermal gradients and increasing compactness. CryoCMOS technology leverages the CMOS fabrication infrastructure and exploits the continuous effort of miniaturization that has sustained Moore’s Law for over 50 years. Such approach is believed to enable the growth of the number of qubits operating in a fault-tolerant fashion, paving the way to scalable quantum computing machines. },
  keywords = {(de)coherence, CryoCMOS, cryogenics, error-correcting loop, fault-tolerant computing, quantum computation, quantum micro-architecture, qubit},
  }

• X. Fu, L. Riesebos, L. Lao, C. G. Almudever, F. Sebastiano, R. Versluis, E. Charbon, and K. Bertels, "A Heterogeneous Quantum Computer Architecture," in Proceedings of the ACM International Conference on Computing Frontiers, New York, NY, USA, 2016, pp. 323-330.
  [Abstract] [Bibtex]
  

  In this paper, we present a high level view of the heterogeneous quantum computer architecture as any future quantum computer will consist of both a classical and quantum computing part. The classical part is needed for error correction as well as for the execution of algorithms that contain both classical and quantum logic. We present a complete system stack describing the di?erent layers when building a quantum computer. We also present the control logic and corresponding data path that needs to be implemented when executing quantum instructions and conclude by discussing design choices in the quantum plane.

  @inproceedings{mine:computer_frontiers_2016_fu,
  author = {X. Fu and L. Riesebos and L. Lao and C.G. Almudever and F. Sebastiano and R. Versluis and E. Charbon and K. Bertels},
  title = {A Heterogeneous Quantum Computer Architecture},
  booktitle = {Proceedings of the ACM International Conference on Computing Frontiers},
  series = {CF '16},
  year = {2016},
  isbn = {978-1-4503-4128-8},
  location = {Como, Italy},
  pages = {323--330},
  numpages = {8},
  url = {http://doi.acm.org/10.1145/2903150.2906827},
  doi = {10.1145/2903150.2906827},
  acmid = {2906827},
  publisher = {ACM},
  address = {New York, NY, USA},
  abstract = {In this paper, we present a high level view of the heterogeneous quantum computer architecture as any future quantum computer will consist of both a classical and quantum computing part. The classical part is needed for error correction as well as for the execution of algorithms that contain both classical and quantum logic. We present a complete system stack describing the di?erent layers when building a quantum computer. We also present the control logic and corresponding data path that needs to be implemented when executing quantum instructions and conclude by discussing design choices in the quantum plane.},
  keywords = {quantum computer (micro-)architecture},
  }

• L. Song, H. Homulle, E. Charbon, and F. Sebastiano, "Characterization of bipolar transistors for cryogenic temperature sensors in standard CMOS," in IEEE Sensors 2016, 2016, pp. 1-3.
  [Abstract] [Bibtex]
  

  This paper presents the cryogenic characterization of the bipolar substrate PNPs that are typically employed as sensing elements in CMOS integrated temperature sensors. PNPs realized in a standard 160-nm CMOS technology were characterized over the temperature range from 7 K to 294 K. Although PNP non-idealities, such as finite current gain and parasitic base resistance, deteriorate at lower temperature, device operation similar to room temperature is observed down to 70 K, while operation at lower temperatures is limited by carrier freeze-out in the base region and limited current gain. These results demonstrate the feasibility of temperature sensors in standard CMOS at cryogenic temperature.

  @inproceedings{mine:ieee_sensor_2016_lin_song,
  author = {Lin Song and Harald Homulle and Edoardo Charbon and Fabio Sebastiano},
  title = "Characterization of bipolar transistors for cryogenic temperature sensors in standard {CMOS}",
  booktitle = "{IEEE} Sensors 2016",
  pages={1-3},
  abstract={This paper presents the cryogenic characterization of the bipolar substrate PNPs that are typically employed as sensing elements in CMOS integrated temperature sensors. PNPs realized in a standard 160-nm CMOS technology were characterized over the temperature range from 7 K to 294 K. Although PNP non-idealities, such as finite current gain and parasitic base resistance, deteriorate at lower temperature, device operation similar to room temperature is observed down to 70 K, while operation at lower temperatures is limited by carrier freeze-out in the base region and limited current gain. These results demonstrate the feasibility of temperature sensors in standard CMOS at cryogenic temperature.},
  keywords={CMOS integrated circuits;bipolar transistors;cryogenics;temperature sensors;CMOS integrated temperature sensors;bipolar substrate PNP;bipolar transistors;carrier freeze-out;cryogenic temperature sensors;finite current gain;parasitic base resistance;size 160 nm;standard CMOS;temperature 7 K to 298 K;CMOS technology;Cryogenics;Standards;Substrates;Temperature distribution;Temperature sensors;CMOS;cryogenics;substrate bipolar transistors;temperature sensors},
  doi={10.1109/ICSENS.2016.7808759},
  year = {2016},
  month= Oct,
  location = {Orlando, FL}
  }

• L. Pedalá, U. Sönmez, F. Sebastiano, K. A. A. Makinwa, K. Nagaraj, and J. Park, "An Oxide Electrothermal Filter in Standard CMOS," in 2016 IEEE Sensors, 2016.
  [Abstract] [Bibtex]
  

  Due to their relatively stable phase shift over temperature, electrothermal filters (ETFs) with an oxide heat path have been used as on-chip phase references, e.g. for thermal diffusivity (TD) temperature sensors. However, previous oxide ETFs were limited to SOI processes, whose deep-trench isolation could be used to create an oxide-dominated heat path. This paper describes, for the first time, an oxide ETF realized in a bulk CMOS process. It achieves a phase spread of 0.6% (3 σ, no trim) from -40 °C to 125 °C. When used as a reference for a TD temperature sensor, this translates into a temperature sensing spread of ±2.7 °C (3 σ, no trim). This is 1.8 times less than the spread reported for SOI implementations, making the CMOS variant not only feasible, but also competitive.

  @inproceedings{mine:ieee_sensor_2016_pedala,
  author = {Lorenzo Pedal\'{a} and Ugur Sönmez and Fabio Sebastiano and Kofi A.A. Makinwa and K. Nagaraj and J. Park},
  title = {An Oxide Electrothermal Filter in Standard CMOS},
  booktitle = {2016 IEEE Sensors},
  year = {2016},
  organization = {IEEE},
  abstract={Due to their relatively stable phase shift over temperature, electrothermal filters (ETFs) with an oxide heat path have been used as on-chip phase references, e.g. for thermal diffusivity (TD) temperature sensors. However, previous oxide ETFs were limited to SOI processes, whose deep-trench isolation could be used to create an oxide-dominated heat path. This paper describes, for the first time, an oxide ETF realized in a bulk CMOS process. It achieves a phase spread of 0.6% (3 σ, no trim) from -40 °C to 125 °C. When used as a reference for a TD temperature sensor, this translates into a temperature sensing spread of ±2.7 °C (3 σ, no trim). This is 1.8 times less than the spread reported for SOI implementations, making the CMOS variant not only feasible, but also competitive.},
  keywords={CMOS integrated circuits;elemental semiconductors;silicon;silicon-on-insulator;temperature measurement;temperature sensors;ETF;SOI processing;Si;TD temperature sensor;bulk standard CMOS process;deep-trench isolation;on-chip phase reference;oxide electrothermal filter;oxide-dominated heat path;temperature -40 degC to 125 degC;thermal diffusivity temperature sensor;Decision support systems;Electronic mail;Heating;Standards;System-on-chip;Temperature sensors;electrothermal filter;phase domain sigma delta ADC;self-referenced;temperature sensor;thermal diffusivity},
  doi={10.1109/ICSENS.2016.7808512},
  month={Oct},
  }

• E. Charbon, F. Sebastiano, A. Vladimirescu, H. Homulle, S. Visser, L. Song, and R. M. Incandela, "Cryo-CMOS for quantum computing," in Proc. 2016 IEEE International Electron Devices Meeting (IEDM), 2016, p. 13.5.1-13.5.4.
  [Abstract] [Bibtex]
  

  Cryogenic CMOS, or cryo-CMOS circuits and systems, are emerging in VLSI design for many applications, in primis quantum computing. Fault-tolerant quantum bits (qubits) in surface code configurations, one of the most accepted implementations in quantum computing, operate in deep sub-Kelvin regime and require scalable classical control circuits. In this paper we advocate the need for a new generation of deep-submicron CMOS circuits operating at deep-cryogenic temperatures to achieve the performance required in a fault-tolerant qubit system. We outline the challenges and limitations of operating CMOS in near-zero Kelvin regimes and we propose solutions. The paper concludes with several examples showing the suitability of integrating fault-tolerant.qubits with CMOS.

  @INPROCEEDINGS{mine:iedm_2016,
  author={Edoardo Charbon and Fabio Sebastiano and Andrei Vladimirescu and Harald Homulle and Stefan Visser and Lin Song and Rosario M. Incandela},
  booktitle={Proc. 2016 IEEE International Electron Devices Meeting (IEDM)},
  title={Cryo-CMOS for quantum computing},
  year={2016},
  volume={},
  number={},
  pages={13.5.1-13.5.4},
  abstract={Cryogenic CMOS, or cryo-CMOS circuits and systems, are emerging in VLSI design for many applications, in primis quantum computing. Fault-tolerant quantum bits (qubits) in surface code configurations, one of the most accepted implementations in quantum computing, operate in deep sub-Kelvin regime and require scalable classical control circuits. In this paper we advocate the need for a new generation of deep-submicron CMOS circuits operating at deep-cryogenic temperatures to achieve the performance required in a fault-tolerant qubit system. We outline the challenges and limitations of operating CMOS in near-zero Kelvin regimes and we propose solutions. The paper concludes with several examples showing the suitability of integrating fault-tolerant.qubits with CMOS.},
  keywords={CMOS integrated circuits;VLSI;cryogenic electronics;fault tolerance;integrated circuit design;integrated circuit reliability;quantum computing;VLSI design;cryoCMOS;cryogenic CMOS circuits;cryogenic CMOS systems;deep-cryogenic temperatures;fault-tolerant quantum bits;fault-tolerant qubit system;quantum computing;Computers;Fault tolerance;Fault tolerant systems;Field programmable gate arrays;Multiplexing;Quantum computing;Quantum dots},
  doi={10.1109/IEDM.2016.7838410},
  ISSN={},
  month={Dec}}

• M. Turchetti, H. Homulle, F. Sebastiano, G. Ferrari, E. Charbon, and E. Prati, "Tunable single hole regime of a silicon field effect transistor in standard CMOS technology," Applied Physics Express, vol. 9, iss. 1, p. 14001, 2016.
  [Abstract] [Bibtex]
  

  The electrical properties of a Single Hole Field Effect Transistor (SH-FET) based on CMOS technology are analyzed in a cryogenic environment. Few electron?hole Coulomb diamonds are observed using quantum transport spectroscopy measurements, down to the limit of single hole transport. Controlling the hole filling of the SH-FET is made possible by biasing the top gate, while the bulk contact is employed as a back gate that tunes the hole state coupling with the contacts and their distance from the interface. We compare the cryogenic Coulomb blockade regime with the room temperature regime, where the device operation is similar to that of a standard p-MOSFET.

  @article{mine:APS_2015,
  author={Marco Turchetti and Harald Homulle and Fabio Sebastiano and Giorgio Ferrari and Edoardo Charbon and Enrico Prati},
  title={Tunable single hole regime of a silicon field effect transistor in standard {CMOS} technology},
  journal={Applied Physics Express},
  volume={9},
  number={1},
  pages={014001},
  url={http://stacks.iop.org/1882-0786/9/i=1/a=014001},
  doi={10.7567/APEX.9.014001},
  year={2016},
  abstract={The electrical properties of a Single Hole Field Effect Transistor (SH-FET) based on CMOS technology are analyzed in a cryogenic environment. Few electron?hole Coulomb diamonds are observed using quantum transport spectroscopy measurements, down to the limit of single hole transport. Controlling the hole filling of the SH-FET is made possible by biasing the top gate, while the bulk contact is employed as a back gate that tunes the hole state coupling with the contacts and their distance from the interface. We compare the cryogenic Coulomb blockade regime with the room temperature regime, where the device operation is similar to that of a standard p-MOSFET.}
  }

• S. Drago, F. Sebastiano, D. M. W. Leenaerts, L. J. Breems, and B. Nauta, "Frequency synthesiser," United States patent , 9240772 B2 , 2016.
  [Bibtex]

  @patent{mine:patent_pll_us,
  author=" Salvatore Drago and Fabio Sebastiano and Domine M.W. Leenaerts and Lucien J. Breems and Bram Nauta",
  title="Frequency synthesiser",
  nationality= "United States",
  number="9240772 B2",
  day="19",
  month=jan,
  year= "2016",
  }

• B. Gönen, F. Sebastiano, K. A. A. Makinwa, and R. H. M. van Veldhoven, "Efficient analog to digital converter," Europe patent , 9325340 , 2016.
  [Bibtex]

  @patent{mine:patent_zoomadc_us,
  author={Burak {Gönen} and Fabio Sebastiano and Kofi A. A. Makinwa and Robert H. M. van Veldhoven},
  title="Efficient analog to digital converter",
  nationality= "Europe",
  number="9325340",
  day="26",
  month=apr,
  year= "2016",
  }

2015

• R. Quan, U. Sonmez, and K. M. A. A. Fabio Sebastiano and, "A 4600µm² 1.5°C (3σ) 0.9kS/s thermal-diffusivity temperature sensor with VCO-based readout," in International Solid-state Circuits Conference Digest of Technical Papers, San Francisco, CA, 2015, pp. 488-489.
  [Abstract] [Bibtex]
  

  This paper presents a highly digital thermal-diffusivity temperature sensor in 0.16µm CMOS for SoC thermal monitoring. The sensor occupies only 4600µm², which is the smallest for designs above 32nm and is one of the smallest ever reported. It also achieves ±1.5°C (3σ, single trim) inaccuracy and 0.6$^circ$C resolution at a 0.9kS/s sampling rate. This small area implementation is mainly enabled by the adoption of a VCO-based phase-domain ADC whose area is 70% digital.

  @INPROCEEDINGS{mine:isscc_2015_TD_sensor,
  author={Rui Quan and Ugur Sonmez and Fabio Sebastiano and, Kofi A.A. Makinwa},
  booktitle={International Solid-state Circuits Conference Digest of Technical Papers},
  address="San Francisco, CA",
  title={A 4600µm² 1.5°C (3σ) 0.9{kS/s} thermal-diffusivity temperature sensor with VCO-based readout},
  year={2015},
  month={Feb},
  pages={488 - 489},
  abstract={This paper presents a highly digital thermal-diffusivity temperature sensor in 0.16µm CMOS for SoC thermal monitoring. The sensor occupies only 4600µm², which is the smallest for designs above 32nm and is one of the smallest ever reported. It also achieves ±1.5°C (3σ, single trim) inaccuracy and 0.6$^circ$C resolution at a 0.9kS/s sampling rate. This small area implementation is mainly enabled by the adoption of a VCO-based phase-domain ADC whose area is 70% digital.},
  keywords={Accuracy;CMOS integrated circuits;Modulation;Radiation detectors;Temperature sensors},
  doi={10.1109/ISSCC.2015.7063139},}

• J. Angevare, L. Pedalà, U. Sonmez, F. Sebastiano, and K. A. A. Makinwa, "A 2800-µm² Thermal-Diffusivity Temperature Sensor with VCO-Based Readout in 160-nm CMOS," in Asian Solid-state Circuits Conference Digest of Technical Papers, Xiamen, China, 2015, pp. 1-4.
  [Abstract] [Bibtex]
  

  A highly digital temperature sensor based on the temperature-dependent thermal diffusivity of bulk silicon has been realized in a standard 160-nm CMOS process. The sensor achieves an inaccuracy of ±2.9°C (3a) from -35°C to 125°C with no trimming and ±1.2°C (3a) after a single-point trim, while achieving a resolution of 0.47°C (rms) at 1 kSa/s. Its compact area (2800 µm2) is enabled by the adoption of a VCO-based phase-domain ADC. Since 53% of the sensor area is occupied by digital circuitry, the sensor can be easily ported to more advanced CMOS technologies with further area reduction, which makes it well suited for thermal monitoring in microprocessors and other systems-on-chip.

  @INPROCEEDINGS{mine:asscc_2015_TD_sensor,
  author={Jan Angevare and Lorenzo Pedalà and Ugur Sonmez and Fabio Sebastiano and Kofi A.A. Makinwa},
  booktitle={Asian Solid-state Circuits Conference Digest of Technical Papers},
  address="Xiamen, China",
  title="A 2800-µm² Thermal-Diffusivity Temperature Sensor with {VCO}-Based Readout in 160-nm {CMOS}",
  year={2015},
  pages={1-4},
  abstract={A highly digital temperature sensor based on the temperature-dependent thermal diffusivity of bulk silicon has been realized in a standard 160-nm CMOS process. The sensor achieves an inaccuracy of ±2.9°C (3a) from -35°C to 125°C with no trimming and ±1.2°C (3a) after a single-point trim, while achieving a resolution of 0.47°C (rms) at 1 kSa/s. Its compact area (2800 µm2) is enabled by the adoption of a VCO-based phase-domain ADC. Since 53% of the sensor area is occupied by digital circuitry, the sensor can be easily ported to more advanced CMOS technologies with further area reduction, which makes it well suited for thermal monitoring in microprocessors and other systems-on-chip.},
  keywords={CMOS digital integrated circuits;analogue-digital conversion;computerised monitoring;digital readout;temperature sensors;thermal diffusivity;voltage-controlled oscillators;VCO-based phase-domain ADC;VCO-based readout;bulk silicon;digital circuitry;highly digital temperature sensor;microprocessors;size 160 nm;standard CMOS process;systems-on-chip;temperature -35 degC to 125 degC;temperature-dependent thermal diffusivity;thermal monitoring;CMOS integrated circuits;CMOS process;Heating;Radiation detectors;Temperature measurement;Temperature sensors},
  doi={10.1109/ASSCC.2015.7387444},
  month={Nov}}

• W. Brevet, F. Sebastiano, and K. A. A. Makinwa, "A 25mW Smart CMOS Wind Sensor with Corner Heaters," in 41st Annual Conference of IEEE Industrial Electronics Society, Yokohama, Japan, 2015, pp. 1194-1199.
  [Abstract] [Bibtex]
  

  A smart CMOS thermal wind sensor has been optimized for commercial use. Optimizing the sensor chip's thermal design resulted in better area efficiency and improved thermal dynamics with respect to prior work. The latter simplifies the off-chip decimation of the sensor's bitstream outputs. Moreover, by realizing more logic on-chip, the number of bond wires has been reduced by 33%, to 8, thus reducing manufacturing costs. Fabricated in a standard 0.7µm CMOS process, the sensor chip occupies 4×4mm2 and consumes 25mW of heating power, while achieving an inaccuracy of ±6% (speed) and ±2° (direction), for wind speeds between 4 and 25m/s.

  @INPROCEEDINGS{mine:iecon_2015_wind_sensor,
  author={Wouter Brevet and Fabio Sebastiano and Kofi A.A. Makinwa},
  booktitle={41st Annual Conference of IEEE Industrial Electronics Society},
  address="Yokohama, Japan",
  title="A 25m{W} Smart {CMOS} Wind Sensor with Corner Heaters",
  pages={001194-001199},
  abstract={A smart CMOS thermal wind sensor has been optimized for commercial use. Optimizing the sensor chip's thermal design resulted in better area efficiency and improved thermal dynamics with respect to prior work. The latter simplifies the off-chip decimation of the sensor's bitstream outputs. Moreover, by realizing more logic on-chip, the number of bond wires has been reduced by 33%, to 8, thus reducing manufacturing costs. Fabricated in a standard 0.7µm CMOS process, the sensor chip occupies 4×4mm2 and consumes 25mW of heating power, while achieving an inaccuracy of ±6% (speed) and ±2° (direction), for wind speeds between 4 and 25m/s.},
  keywords={CMOS integrated circuits;heating;intelligent sensors;wind power;wires (electric);corner heater;logic on-chip;power 25 mW;sensor bitstream output off-chip decimation;sensor chip thermal design;size 0.7 mum;smart CMOS thermal wind sensor;standard CMOS process;Clocks;Frequency modulation;Heating;Thermal sensors;Wind speed;Electrothermal filter (ETF);Smart wind sensor;Thermal sensors;thermal sigma-delta modulatiom},
  doi={10.1109/IECON.2015.7392262},
  month={Nov},
  year="2015"
  }

• F. Sebastiano, L. J. Breems, and R. Roovers, "Automatic Common-mode Rejection Calibration," Europe patent , 2195922 B1 , 2015.
  [Bibtex]

  @patent{mine:patent_cmrr_ep,
  author="Fabio Sebastiano and Lucien J. Breems and Raf Roovers",
  title="Automatic Common-mode Rejection Calibration",
  nationality= "Europe",
  number="2195922 B1",
  day="4",
  month=mar,
  year= "2015",
  }

2014

• F. Sebastiano, F. Butti, R. H. M. van Veldhoven, and P. Bruschi, "A 0.07mm² 2-Channel Instrumentation Amplifier with 0.1% Gain Matching in 0.16µm CMOS," in International Solid-state Circuits Conference Digest of Technical Papers, San Francisco, CA, 2014, pp. 294-295.
  [Abstract] [Bibtex]
  

  Extremely small-area sensor front-ends are required for cost-constrained automotive applications. Instrumentation amplifiers (IA) for such front-ends must process multi-channel sensor outputs and provide gain matching over the channels for proper sensor operation. Angular sensors are a typical example, in which the sine and cosine outputs of a resistive magnetic sensor must be processed with adequate gain matching to avoid unacceptable angular errors. This paper presents a 2-channel instrumentation amplifier in 0.16µm CMOS with 0.1% gain matching and occupying 0.035mm2 per channel. This represents a 13.3x area improvement with respect to state-of-the-art designs with similar gain accuracy [1]-[4], while maintaining low noise (18.7nV/√Hz), low offset (17µV) and high power efficiency (NEF=12.9). The accurate gain matching in a limited area is enabled by the adoption of a dynamic element matching (DEM) scheme and by the use of a high chopping frequency.

  @inproceedings{mine:isscc_2014_amplifier,
  author = "Fabio Sebastiano and Federico Butti and Robert H.M. van Veldhoven and Paolo Bruschi",
  month = feb # {9--13},
  year = "2014",
  title="A 0.07mm² 2-Channel Instrumentation Amplifier with 0.1% Gain Matching in 0.16µm {CMOS}",
  booktitle={International Solid-state Circuits Conference Digest of Technical Papers},
  pages={294 - 295},
  abstract={Extremely small-area sensor front-ends are required for cost-constrained automotive applications. Instrumentation amplifiers (IA) for such front-ends must process multi-channel sensor outputs and provide gain matching over the channels for proper sensor operation. Angular sensors are a typical example, in which the sine and cosine outputs of a resistive magnetic sensor must be processed with adequate gain matching to avoid unacceptable angular errors. This paper presents a 2-channel instrumentation amplifier in 0.16µm CMOS with 0.1% gain matching and occupying 0.035mm2 per channel. This represents a 13.3x area improvement with respect to state-of-the-art designs with similar gain accuracy [1]-[4], while maintaining low noise (18.7nV/√Hz), low offset (17µV) and high power efficiency (NEF=12.9). The accurate gain matching in a limited area is enabled by the adoption of a dynamic element matching (DEM) scheme and by the use of a high chopping frequency.},
  keywords={CMOS integrated circuits;instrumentation amplifiers;2-channel instrumentation amplifier;CMOS;DEM scheme;IA;angular sensors;cosine outputs;cost-constrained automotive applications;dynamic element matching scheme;gain matching;high chopping frequency;multichannel sensor outputs;resistive magnetic sensor;sensor front-ends;sensor operation;size 0.16 mum;voltage 17 muV;Accuracy;CMOS integrated circuits;Gain measurement;Instruments;Noise measurement;Solid state circuits;Switches},
  address="San Francisco, CA",
  doi={10.1109/ISSCC.2014.6757440},
  ISSN={0193-6530},
  }

• U. Sonmez, R. Quan, F. Sebastiano, and K. A. A. Makinwa, "A 0.008-mm² area-optimized thermal-diffusivity-based temperature sensor in 160-nm CMOS for SoC thermal monitoring," in Proc. European Solid-State Circuits Conference, Venice, Italy, 2014, pp. 395-398.
  [Abstract] [Bibtex]
  

  An array of temperature sensors based on the temperature-dependent thermal diffusivity of bulk silicon has been realized in a standard 160-nm CMOS process. The sensors achieve an inaccuracy of ±2.4 °C (3σ) from -40 to 125 °C with no trimming and ±0.65 °C (3σ) with a one temperature trim. Each sensor occupies 0.008 mm², and achieves a resolution of 0.21 °C (rms) at 1 kSa/s. This combination of accuracy, speed, and small size makes such sensors well suited for thermal monitoring in microprocessors and other systems-on-chip.

  @INPROCEEDINGS{mine:esscirc_2014_TD_sensor,
  author = "Ugur Sonmez and Rui Quan and Fabio Sebastiano and Kofi. A. A. Makinwa",
  booktitle="Proc. {European Solid-State Circuits Conference}",
  title={A 0.008-mm² area-optimized thermal-diffusivity-based temperature sensor in 160-nm {CMOS} for {SoC} thermal monitoring},
  year={2014},
  month=sep # {22--26},
  address="Venice, Italy",
  pages={395-398},
  abstract={An array of temperature sensors based on the temperature-dependent thermal diffusivity of bulk silicon has been realized in a standard 160-nm CMOS process. The sensors achieve an inaccuracy of ±2.4 °C (3σ) from -40 to 125 °C with no trimming and ±0.65 °C (3σ) with a one temperature trim. Each sensor occupies 0.008 mm², and achieves a resolution of 0.21 °C (rms) at 1 kSa/s. This combination of accuracy, speed, and small size makes such sensors well suited for thermal monitoring in microprocessors and other systems-on-chip.},
  keywords={CMOS integrated circuits;system-on-chip;temperature measurement;temperature sensors;thermal diffusivity;SoC thermal monitoring;area-optimized thermal-diffusivity-based temperature sensor;bulk silicon;microprocessors;size 160 nm;standard CMOS process;systems-on-chip;temperature-dependent thermal diffusivity;thermal monitoring;Accuracy;Heating;System-on-chip;Temperature measurement;Temperature sensors},
  doi={10.1109/ESSCIRC.2014.6942105},
  ISSN={1930-8833}
  }

• F. Sebastiano, R. H. M. van Veldhoven, and S. Ersoy, "Modulator with high signal to noise ratio," Europe patent , patent request 14160161 , 2014.
  [Bibtex]

  @patent{mine:patent_magnetic4_ep,
  author="Fabio Sebastiano and Robert H.M. van Veldhoven and Selcuk Ersoy",
  title="Modulator with high signal to noise ratio",
  nationality= "Europe",
  number="14160161",
  day="14",
  month=mar,
  year= "2014",
  type="patent request"
  }

2013

• S. Ersoy, R. H. M. van Veldhoven, F. Sebastiano, and K. Reimann, "A 0.25mm² AC-Biased MEMS Microphone Interface with 58dBA SNR," in International Solid-state Circuits Conference Digest of Technical Papers, San Francisco, CA, 2013, pp. 382-383.
  [Abstract] [Bibtex]
  

  Capacitive MEMS microphone roadmaps are mainly driven by increasing SNR and reducing size/cost. This requires smaller microphones, ASICs with lower noise and smaller area, and cheaper packaging. Because of fundamental limitations, traditional DC-biased microphones will have difficulty following these trends. This paper proposes an AC-biasing scheme, which leads to a significant reduction in ASIC size and module packaging cost.

  @inproceedings{mine:isscc_2013_selcuk,
  author = "Sel\c{c}uk Ersoy and Robert H.M. van Veldhoven and Fabio Sebastiano and Klaus Reimann",
  month = feb # {17--21},
  year = "2013",
  title="A 0.25mm² {AC}-Biased {MEMS} Microphone Interface with {58dBA SNR}",
  booktitle={International Solid-state Circuits Conference Digest of Technical Papers},
  pages="382-383",
  address="San Francisco, CA",
  abstract={Capacitive MEMS microphone roadmaps are mainly driven by increasing SNR and reducing size/cost. This requires smaller microphones, ASICs with lower noise and smaller area, and cheaper packaging. Because of fundamental limitations, traditional DC-biased microphones will have difficulty following these trends. This paper proposes an AC-biasing scheme, which leads to a significant reduction in ASIC size and module packaging cost.},
  keywords={AC machines;DC machines;capacitance;electronics packaging;micromechanical devices;microphones;AC-biased MEMS microphone interface;AC-biasing scheme;ASIC size reduction;DC-biased microphone;SNR;capacitive MEMS microphone roadmap;module packaging cost;noise},
  doi={10.1109/ISSCC.2013.6487779},
  ISSN={0193-6530}
  }

• F. Sebastiano, L. J. Breems, and K. A. A. Makinwa, Mobility-based Time References for Wireless Sensor Networks, Springer, 2013.
  [Abstract] [Bibtex]
  

  This book describes the use of low-power low-cost and extremely small radios to provide essential time reference for wireless sensor networks. The authors explain how to integrate such radios in a standard CMOS process to reduce both cost and size, while focusing on the challenge of designing a fully integrated time reference for such radios. To enable the integration of the time reference, system techniques are proposed and analyzed, several kinds of integrated time references are reviewed, and mobility-based references are identified as viable candidates to provide the required accuracy at low-power consumption. Practical implementations of a mobility-based oscillator and a temperature sensor are also presented, which demonstrate the required accuracy over a wide temperature range, while drawing 51-µW from a 1.2-V supply in a 65-nm CMOS process.

  @book{mine:book_mobility,
  author = "Fabio Sebastiano and Lucien J. Breems and Kofi A.A. Makinwa",
  title = "Mobility-based Time References for Wireless Sensor Networks",
  publisher = "Springer",
  year = "2013",
  abstract  = {This book describes the use of low-power low-cost and extremely small radios to provide essential time reference for wireless sensor networks. The authors explain how to integrate such radios in a standard CMOS process to reduce both cost and size, while focusing on the challenge of designing a fully integrated time reference for such radios. To enable the integration of the time reference, system techniques are proposed and analyzed, several kinds of integrated time references are reviewed, and mobility-based references are identified as viable candidates to provide the required accuracy at low-power consumption. Practical implementations of a mobility-based oscillator and a temperature sensor are also presented, which demonstrate the required accuracy over a wide temperature range, while drawing 51-µW from a 1.2-V supply in a 65-nm CMOS process.}
  }

• F. Sebastiano, S. Drago, L. J. Breems, and D. M. W. Leenaerts, "Method and system for impulse radio wakeup," United States patent , 8620394 B2 , 2013.
  [Bibtex]

  @patent{mine:patent_ir2_us,
  author="Fabio Sebastiano and Salvatore Drago and Lucien J. Breems and Domine M.W. Leenaerts ",
  title="Method and system for impulse radio wakeup",
  nationality= "United States",
  number="8620394 B2",
  day="31",
  month=dec,
  year= "2013",
  }

2012

• F. Sebastiano, L. J. Breems, and R. Roovers, "Automatic Common-mode Rejection Calibration," United States patent , 8174416 , 2012.
  [Bibtex]

  @patent{mine:patent_cmrr_us,
  author="Fabio Sebastiano and Lucien J. Breems and Raf Roovers",
  title="Automatic Common-mode Rejection Calibration",
  nationality= "United States",
  number="8174416",
  day="8",
  month=may,
  year= "2012"
  }

• S. Drago, F. Sebastiano, D. M. W. Leenaerts, L. J. Breems, and B. Nauta, "Frequency synthesiser," China patent , patent request 102369665 A , 2012.
  [Bibtex]

  @patent{mine:patent_pll_cn,
  author=" Salvatore Drago and Fabio Sebastiano and Domine M.W. Leenaerts and Lucien J. Breems and Bram Nauta",
  title="Frequency synthesiser",
  nationality= "China",
  number="102369665 A",
  day="7",
  month=mar,
  year= "2012",
  type="patent request"
  }

2011

• F. Sebastiano, L. J. Breems, K. Makinwa, S. Drago, D. M. W. Leenaerts, and B. Nauta, "Effects of Packaging and Process Spread on a Mobility-Based Frequency Reference in 0.16-µm CMOS," in Proc. European Solid-State Circuits Conference, Helsinki, Finland, 2011, pp. 511-514.
  [Abstract] [Bibtex]
  

  In this paper, we explore the robustness of frequency references based on the electron mobility in a MOS transistor by implementing them with both thin-oxide and thick-oxide MOS transistors in a 0.16-µm CMOS process, and by testing samples packaged in both ceramic and plastic packages. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for applications requiring fully integrated solutions, such as Wireless Sensor Networks. Over the temperature range from -55 °C to 125 °C, its frequency spread is less than ±1% (3σ) after a one-point trim. Fabricated in a baseline 0.16-µm CMOS process, the 50 kHz frequency reference occupies 0.06 mm² and, at room temperature, its consumption with a 1.2-V supply is less than 17 µW.

  @INPROCEEDINGS{mine:esscirc_2011_mobility_cmos14,
  author = "Fabio Sebastiano and Lucien J. Breems and Kofi Makinwa and Salvatore Drago and Domine M. W. Leenaerts and Bram Nauta",
  booktitle="Proc. {European Solid-State Circuits Conference}",
  title="Effects of Packaging and Process Spread on a Mobility-Based Frequency Reference in 0.16-µm {CMOS}",
  year={2011},
  month=sep # {12-16},
  address="Helsinki, Finland",
  pages={511 - 514},
  abstract={In this paper, we explore the robustness of frequency references based on the electron mobility in a MOS transistor by implementing them with both thin-oxide and thick-oxide MOS transistors in a 0.16-µm CMOS process, and by testing samples packaged in both ceramic and plastic packages. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for applications requiring fully integrated solutions, such as Wireless Sensor Networks. Over the temperature range from -55 °C to 125 °C, its frequency spread is less than ±1% (3σ) after a one-point trim. Fabricated in a baseline 0.16-µm CMOS process, the 50 kHz frequency reference occupies 0.06 mm² and, at room temperature, its consumption with a 1.2-V supply is less than 17 µW.},
  keywords={CMOS integrated circuits;MOSFET;ceramic packaging;electron mobility;low-power electronics;plastic packaging;reference circuits;wireless sensor networks;CMOS process;ceramic packages;electron mobility;frequency 50 kHz;low-voltage low-power circuit;mobility-based frequency reference;off-chip components;packaging;plastic packages;process spread;size 0.16 mum;temperature -55 degC to 125 degC;temperature 293 K to 298 K;thick-oxide MOS transistors;thin-oxide MOS transistors;voltage 1.2 V;wireless sensor networks;Accuracy;Ceramics;Oscillators;Plastics;Temperature distribution;Temperature measurement;Transistors},
  doi={10.1109/ESSCIRC.2011.6044934},
  ISSN={1930-8833}
  }

• F. Sebastiano, L. J. Breems, K. Makinwa, S. Drago, D. M. W. Leenaerts, and B. Nauta, "A 65-nm CMOS temperature-compensated mobility-based frequency reference for Wireless Sensor Networks," IEEE J. Solid-State Circuits, vol. 46, iss. 7, pp. 1544-1552, 2011.
  [Abstract] [Bibtex]
  

  A temperature-compensated CMOS frequency reference based on the electron mobility in a MOS transistor is presented. Over the temperature range from -55 °C to 125 °C, the frequency spread of the complete reference is less than ±0.5% after a two-point trim and less than ±2.7% after a one-point trim. These results make it suitable for use in Wireless Sensor Network nodes. Fabricated in a baseline 65-nm CMOS process, the 150 kHz frequency reference occupies 0.2 mm² and draws 42.6 µA from a 1.2-V supply at room temperature.

  @ARTICLE{mine:jssc_2011_mobility_comp,
  author = "Fabio Sebastiano and Lucien J. Breems and Kofi Makinwa and Salvatore Drago and Domine M. W. Leenaerts and Bram Nauta",
  journal=IEEE_J_JSSC,
  title="A 65-nm {CMOS} temperature-compensated mobility-based frequency reference for Wireless Sensor Networks",
  year={2011},
  month=jul,
  volume={46},
  number={7},
  pages={1544 - 1552},
  abstract={A temperature-compensated CMOS frequency reference based on the electron mobility in a MOS transistor is presented. Over the temperature range from -55 °C to 125 °C, the frequency spread of the complete reference is less than ±0.5% after a two-point trim and less than ±2.7% after a one-point trim. These results make it suitable for use in Wireless Sensor Network nodes. Fabricated in a baseline 65-nm CMOS process, the 150 kHz frequency reference occupies 0.2 mm² and draws 42.6 µA from a 1.2-V supply at room temperature.},
  keywords={CMOS integrated circuits;compensation;electron mobility;wireless sensor networks;MOS transistor;current 42.6 muA;electron mobility;mobility-based frequency reference;size 65 nm;temperature -55 degC to 125 degC;temperature-compensated CMOS frequency reference;two-point trim;voltage 1.2 V;wireless sensor networks;Accuracy;Frequency conversion;Oscillators;Temperature;Temperature measurement;Temperature sensors;Wireless sensor networks;CMOS integrated circuits;Charge carrier mobility;MOSFET;crystal-less clock;frequency reference;low voltage;sigma-delta modulation;smart sensors;temperature compensation;temperature sensors;ultra-low power;wireless sensor networks},
  doi={10.1109/JSSC.2011.2143630},
  ISSN={0018-9200}
  }

• Q. Fan, F. Sebastiano, J. H. Huijsing, and K. A. A. Makinwa, "A 1.8 µW 60 nV/√Hz Capacitively-Coupled Chopper Instrumentation Amplifier in 65 nm CMOS for Wireless Sensor Nodes," IEEE J. Solid-State Circuits, vol. 46, iss. 7, pp. 1534-1543, 2011.
  [Abstract] [Bibtex]
  

  This paper presents a low-power precision instrumentation amplifier intended for use in wireless sensor nodes. It employs a capacitively-coupled chopper topology to achieve a rail-to-rail input common-mode range as well as high power efficiency. A positive feedback loop is employed to boost its input impedance, while a ripple reduction loop suppresses the chopping ripple. To facilitate bio-potential sensing, an optional DC servo loop may be employed to suppress electrode offset. The IA achieves 1 µV offset, 0.16% gain inaccuracy, 134 dB CMRR, 120 dB PSRR and a noise efficiency factor of 3.3. The instrumentation amplifier was implemented in a 65 nm CMOS technology. It occupies only 0.1 mm² chip area (0.2 mm² with the DC servo loop) and consumes 1.8 µA current (2.1 µA with the DC servo loop) from a 1 V supply.

  @ARTICLE{mine:jssc_2011_qinwen,
  author="Qinwen Fan and Fabio Sebastiano and Johan H. Huijsing and Kofi A.A. Makinwa",
  journal=IEEE_J_JSSC,
  title="A 1.8 µ{W} 60 nV/√{Hz} Capacitively-Coupled Chopper Instrumentation Amplifier in 65 nm {CMOS} for Wireless Sensor Nodes",
  year={2011},
  month=jul,
  volume={46},
  number={7},
  pages={1534 - 1543},
  abstract={This paper presents a low-power precision instrumentation amplifier intended for use in wireless sensor nodes. It employs a capacitively-coupled chopper topology to achieve a rail-to-rail input common-mode range as well as high power efficiency. A positive feedback loop is employed to boost its input impedance, while a ripple reduction loop suppresses the chopping ripple. To facilitate bio-potential sensing, an optional DC servo loop may be employed to suppress electrode offset. The IA achieves 1 µV offset, 0.16% gain inaccuracy, 134 dB CMRR, 120 dB PSRR and a noise efficiency factor of 3.3. The instrumentation amplifier was implemented in a 65 nm CMOS technology. It occupies only 0.1 mm² chip area (0.2 mm² with the DC servo loop) and consumes 1.8 µA current (2.1 µA with the DC servo loop) from a 1 V supply.},
  keywords={CMOS integrated circuits;choppers (circuits);instrumentation amplifiers;wireless sensor networks;CMOS technology;CMRR;DC servo loop;PSRR;biopotential sensing;capacitively-coupled chopper instrumentation amplifier;chopping ripple;current 1.8 muA;electrode offset suppression;low-power precision instrumentation amplifier;noise efficiency factor;positive feedback loop;power 1.8 muW;rail-to-rail input common-mode range;ripple reduction loop;size 65 nm;voltage 1 V;wireless sensor nodes;Capacitors;Choppers;Impedance;Noise;Sensors;Topology;Wireless sensor networks;Bio-signal sensing;chopping;high power efficiency;low offset;low power;precision amplifier;wireless sensor nodes},
  doi={10.1109/JSSC.2011.2143610},
  ISSN={0018-9200}
  }

2010

• F. Sebastiano, L. J. Breems, K. Makinwa, S. Drago, D. M. W. Leenaerts, and B. Nauta, "A 1.2V 10µW NPN-based temperature sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3σ) from -70°C to 125°C," in International Solid-state Circuits Conference Digest of Technical Papers, San Francisco, CA, 2010, pp. 312-313.
  [Abstract] [Bibtex]
  

  A temperature sensor utilizing NPN transistors has been realized in a 65 nm CMOS process. It achieves a batch-calibrated inaccuracy of ±0.5°C (3σ) and a trimmed inaccuracy of ±0.2°C (3σ) from -70°C to 125°C The sensor draws 8.3 µA from a 1.2 V supply and occupies an area of 0.1 mm².

  @inproceedings{mine:isscc_2010_temp_sens,
  author = "Fabio Sebastiano and Lucien J. Breems and Kofi Makinwa and Salvatore Drago and Domine M. W. Leenaerts and Bram Nauta",
  month = feb # {7--11},
  year = "2010",
  title = "A {1.2V} {10µW} {NPN}-based temperature sensor in 65nm {CMOS} with an inaccuracy of ±0.2°{C} (3σ) from -70°{C} to 125°{C}",
  booktitle={International Solid-state Circuits Conference Digest of Technical Papers},
  pages="312 - 313",
  address="San Francisco, CA",
  abstract={A temperature sensor utilizing NPN transistors has been realized in a 65 nm CMOS process. It achieves a batch-calibrated inaccuracy of ±0.5°C (3σ) and a trimmed inaccuracy of ±0.2°C (3σ) from -70°C to 125°C The sensor draws 8.3 µA from a 1.2 V supply and occupies an area of 0.1 mm².},
  keywords={CMOS integrated circuits;signal processing equipment;temperature sensors;CMOS technology;batch calibrated inaccuracy;current 8.3 µA;power 10 µW;size 65 nm;temperature -70 C to 125 C;temperature sensor;voltage 1.2 V;CMOS technology;Pipelines;Robustness;Sampling methods;Switches;Tail;Temperature sensors;Testing;Timing;Voltage},
  doi={10.1109/ISSCC.2010.5433895},
  ISSN={0193-6530}
  }

• S. Drago, D. M. W. Leenaerts, F. Sebastiano, L. J. and Breems, K. A. A. Makinwa, and B. Nauta, "A 2.4GHz 830pJ/bit duty-cycled wake-up receiver with -82dBm sensitivity for crystal-less wireless sensor nodes," in International Solid-state Circuits Conference Digest of Technical Papers, San Francisco, CA, 2010, pp. 224-225.
  [Abstract] [Bibtex]
  

  A 65 nm CMOS 2.4 GHz wake-up receiver operating with low-accuracy frequency references has been realized. Robustness to frequency inaccuracy is achieved by employing non-coherent energy detection, broadband-IF heterodyne architecture and impulse-radio modulation. The radio dissipates 415 µW at 500 kb/s and achieves a sensitivity of -82 dBm with an energy efficiency of 830 pJ/bit.

  @INPROCEEDINGS{mine:isscc_2010_wakeup,
  author="Salvatore Drago and Domine M.W. Leenaerts and Fabio Sebastiano and and Lucien J. Breems and Kofi A.A. Makinwa and Bram Nauta",
  booktitle={International Solid-state Circuits Conference Digest of Technical Papers},
  title="A 2.4{GHz} 830{pJ/bit} duty-cycled wake-up receiver with -82dBm sensitivity for crystal-less wireless sensor nodes",
  year={2010},
  month = feb # {7--11},
  pages={224 - 225},
  address="San Francisco, CA",
  abstract={A 65 nm CMOS 2.4 GHz wake-up receiver operating with low-accuracy frequency references has been realized. Robustness to frequency inaccuracy is achieved by employing non-coherent energy detection, broadband-IF heterodyne architecture and impulse-radio modulation. The radio dissipates 415 µW at 500 kb/s and achieves a sensitivity of -82 dBm with an energy efficiency of 830 pJ/bit.},
  keywords={CMOS integrated circuits;UHF integrated circuits;field effect MMIC;radio receivers;ultra wideband communication;wireless sensor networks;CMOS wake up receiver;bit rate 500 kbit/s;broadband IF heterodyne architecture;crystal less wireless sensor nodes;frequency 2.4 GHz;impulse radio modulation;non coherent energy detection;power 415 muW;size 65 nm;Baseband;Bit error rate;Clocks;Filters;Gain measurement;Pulse amplifiers;Radio frequency;Radiofrequency amplifiers;Voltage;Wireless sensor networks},
  doi={10.1109/ISSCC.2010.5433955},
  ISSN={0193-6530}
  }

• F. Sebastiano, L. J. Breems, K. Makinwa, S. Drago, D. M. W. Leenaerts, and B. Nauta, "A 65-nm CMOS temperature-compensated mobility-based frequency reference for Wireless Sensor Networks," in Proc. European Solid-State Circuits Conference, Sevilla, Spain, 2010, pp. 102-105.
  [Abstract] [Bibtex]
  

  For the first time, a temperature-compensated CMOS frequency reference based on the electron mobility in a MOS transistor is presented. Over the temperature range from -55 °C to 125 °C, its frequency spread is less than ±0.5% after a two-point trim and less than ±2.7% after a one-point trim. These results make it suitable for use in Wireless Sensor Network nodes. Fabricated in a baseline 65-nm CMOS process, the 150 kHz frequency reference occupies 0.2 mm² and draws 42.6 µA from a 1.2-V supply at room temperature.

  @INPROCEEDINGS{mine:esscirc_2010_mobility_comp,
  author = "Fabio Sebastiano and Lucien J. Breems and Kofi Makinwa and Salvatore Drago and Domine M. W. Leenaerts and Bram Nauta",
  booktitle="Proc. {European Solid-State Circuits Conference}",
  title="A 65-nm {CMOS} temperature-compensated mobility-based frequency reference for Wireless Sensor Networks",
  year={2010},
  month=sep # {14--16},
  pages={102 - 105},
  address="Sevilla, Spain",
  abstract={For the first time, a temperature-compensated CMOS frequency reference based on the electron mobility in a MOS transistor is presented. Over the temperature range from -55 °C to 125 °C, its frequency spread is less than ±0.5% after a two-point trim and less than ±2.7% after a one-point trim. These results make it suitable for use in Wireless Sensor Network nodes. Fabricated in a baseline 65-nm CMOS process, the 150 kHz frequency reference occupies 0.2 mm² and draws 42.6 µA from a 1.2-V supply at room temperature.},
  keywords={CMOS integrated circuits;MOSFET;electron mobility;wireless sensor networks;CMOS temperature-compensated mobility;MOS transistor;current 42.6 muA;electron mobility;frequency 150 kHz;frequency reference;size 65 nm;temperature -55 C to 125 C;voltage 1.2 V;wireless sensor network;Accuracy;CMOS integrated circuits;Calibration;Oscillators;Temperature measurement;Temperature sensors;Wireless sensor networks},
  doi={10.1109/ESSCIRC.2010.5619792},
  ISSN={1930-8833}
  }

• Q. Fan, F. Sebastiano, J. H. Huijsing, and K. A. A. Makinwa, "A 1.8µW 1-µV-offset capacitively-coupled chopper instrumentation amplifier in 65nm CMOS," in Proc. European Solid-State Circuits Conference, Sevilla, Spain, 2010, pp. 170-173.
  [Abstract] [Bibtex]
  

  This paper describes a precision capacitively-coupled chopper instrumentation amplifier (CCIA). It achieves 1µV offset, 134dB CMRR, 120dB PSRR, 0.16% gain accuracy and a noise efficiency factor (NEF) of 3.1, which is more than 3x better than state-of-the-art. It has a rail-to-rail DC common-mode (CM) input range. Furthermore, a positive feedback loop (PFL) is used to boost the input impedance, and a ripple reduction loop (RRL) is used to reduce the ripple associated with chopping. The CCIA occupies only 0.1mm² in a 65nm CMOS technology. It can operate from a 1V supply, from which it draws only 1.8µA.

  @INPROCEEDINGS{mine:esscirc_2010_qinwen,
  author="Qinwen Fan and Fabio Sebastiano and Johan H. Huijsing and Kofi A.A. Makinwa",
  booktitle="Proc. {European Solid-State Circuits Conference}",
  title="A 1.8µ{W} 1-µV-offset capacitively-coupled chopper instrumentation amplifier in 65nm {CMOS}",
  year={2010},
  month=sep # {14--16},
  address="Sevilla, Spain",
  pages={170 - 173},
  abstract={This paper describes a precision capacitively-coupled chopper instrumentation amplifier (CCIA). It achieves 1µV offset, 134dB CMRR, 120dB PSRR, 0.16% gain accuracy and a noise efficiency factor (NEF) of 3.1, which is more than 3x better than state-of-the-art. It has a rail-to-rail DC common-mode (CM) input range. Furthermore, a positive feedback loop (PFL) is used to boost the input impedance, and a ripple reduction loop (RRL) is used to reduce the ripple associated with chopping. The CCIA occupies only 0.1mm² in a 65nm CMOS technology. It can operate from a 1V supply, from which it draws only 1.8µA.},
  keywords={CMOS integrated circuits;instrumentation amplifiers;CMOS;input impedance;noise efficiency factor;positive feedback loop;precision capacitively-coupled chopper instrumentation amplifier;rail-to-rail DC common-mode input range;ripple reduction loop;size 65 nm;Accuracy;Choppers;Impedance;Instruments;Noise;Resistors;Topology},
  doi={10.1109/ESSCIRC.2010.5619902},
  ISSN={1930-8833}
  }

• Q. Fan, F. Sebastiano, J. H. Huijsing, and K. A. A. Makinwa, "A 2.1 µW Area-Efficient Capacitively-Coupled Chopper Instrumentation Amplifier for ECG Applications in 65 nm CMOS," in Proc. Asian Solid-State Circuits Conference, Beijing, China, 2010, pp. 1-4.
  [Abstract] [Bibtex]
  

  This paper describes a capacitively-coupled chopper instrumentation amplifier for use in electrocardiography (ECG). The amplifier's gain is accurately defined by a capacitive feedback network, while a DC servo loop rejects the DC offset generated by the electrode-tissue interface. The high-pass corner frequency established by the servo loop is realized by an area-efficient switched-capacitor integrator. Additional feedback loops are employed to boost the amplifier's input-impedance to 80 MΩ and to suppress the chopper ripple. Implemented in a 65 nm CMOS technology, the amplifier draws 2.1 µA from a 1 V supply and occupies 0.2 mm².

  @INPROCEEDINGS{mine:asscc_2010_qinwen,
  author="Qinwen Fan and Fabio Sebastiano and Johan H. Huijsing and Kofi A.A. Makinwa",
  booktitle="Proc. {Asian Solid-State Circuits Conference}",
  title="A 2.1 µ{W} Area-Efficient Capacitively-Coupled Chopper Instrumentation Amplifier for ECG Applications in 65 nm {CMOS}",
  year={2010},
  month=nov # {8--10},
  address="Beijing, China",
  pages={1 - 4},
  abstract={This paper describes a capacitively-coupled chopper instrumentation amplifier for use in electrocardiography (ECG). The amplifier's gain is accurately defined by a capacitive feedback network, while a DC servo loop rejects the DC offset generated by the electrode-tissue interface. The high-pass corner frequency established by the servo loop is realized by an area-efficient switched-capacitor integrator. Additional feedback loops are employed to boost the amplifier's input-impedance to 80 MΩ and to suppress the chopper ripple. Implemented in a 65 nm CMOS technology, the amplifier draws 2.1 µA from a 1 V supply and occupies 0.2 mm².},
  keywords={CMOS integrated circuits;amplifiers;biomedical electrodes;choppers (circuits);electrocardiography;CMOS technology;DC servo loop;ECG application;area efficient chopper instrumentation amplifier;capacitive feedback network;capacitively coupled chopper instrumentation amplifier;electrocardiography;electrode-tissue interface;power 2.1 muW;switched capacitor integrator;Choppers;DSL;Earth Observing System;Electrocardiography;Impedance;Instruments;Noise},
  doi={10.1109/ASSCC.2010.5716624}
  }

• S. Drago, D. M. W. Leenaerts, B. Nauta, F. Sebastiano, K. A. A. Makinwa, and L. J. Breems, "A 200 µA Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 45, iss. 7, pp. 1305-1315, 2010.
  [Abstract] [Bibtex]
  

  The design of a duty-cycled PLL (DCPLL) capable of burst mode operation is presented. The proposed DCPLL is a moderately accurate low-power high-frequency synthesizer suitable for use in nodes for wireless sensor networks (WSN). Thanks to a dual loop configuration, the PLL's total frequency error, once in lock, is less than 0.25% from 300 MHz to 1.2 GHz. It employs a fast start-up DCO which enables its operation at duty-cycles as low as 10%. Fabricated in a baseline 65 nm CMOS technology, the DCPLL circuit occupies 0.19 x 0.15 mm² and draws 200 µA from a 1.3 V supply when generating bursts of 1 GHz signal with a 10% duty-cycle.

  @ARTICLE{mine:jssc_2010_pll,
  author="Salvatore Drago and Domine M.W. Leenaerts and Bram Nauta and Fabio Sebastiano and Kofi A.A. Makinwa and Lucien J. Breems",
  journal=IEEE_J_JSSC,
  title="A 200 µ{A} Duty-Cycled {PLL} for Wireless Sensor Nodes in 65 nm {CMOS}",
  year={2010},
  month=jul,
  volume={45},
  number={7},
  pages={1305 - 1315},
  abstract={The design of a duty-cycled PLL (DCPLL) capable of burst mode operation is presented. The proposed DCPLL is a moderately accurate low-power high-frequency synthesizer suitable for use in nodes for wireless sensor networks (WSN). Thanks to a dual loop configuration, the PLL's total frequency error, once in lock, is less than 0.25% from 300 MHz to 1.2 GHz. It employs a fast start-up DCO which enables its operation at duty-cycles as low as 10%. Fabricated in a baseline 65 nm CMOS technology, the DCPLL circuit occupies 0.19 x 0.15 mm² and draws 200 µA from a 1.3 V supply when generating bursts of 1 GHz signal with a 10% duty-cycle.},
  keywords={CMOS integrated circuits;UHF integrated circuits;frequency synthesizers;low-power electronics;phase locked loops;wireless sensor networks;CMOS technology;DCPLL circuit;current 200 muA;duty-cycled PLL;frequency 300 MHz to 1.2 GHz;frequency error;low-power high-frequency synthesizer;size 65 nm;voltage 1.3 V;wireless sensor networks;wireless sensor nodes;Batteries;CMOS technology;Energy consumption;Frequency synthesizers;Integrated circuit technology;Jitter;Oscillators;Phase locked loops;Phase noise;Wireless sensor networks;CMOS;PLL;WSN;duty-cycle;frequency stability;frequency synthesizer;fully integrated;ultra-low-power;wireless sensor networks},
  doi={10.1109/JSSC.2010.2049458},
  ISSN={0018-9200}
  }

• F. Sebastiano, L. J. Breems, K. Makinwa, S. Drago, D. M. W. Leenaerts, and B. Nauta, "A 1.2-V 10-µW NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 0.2 °C (3σ) From -70 °C to 125 °C," IEEE J. Solid-State Circuits, vol. 45, iss. 12, pp. 2591-2601, 2010.
  [Abstract] [Bibtex]
  

  An NPN-based temperature sensor with digital output has been realized in a 65-nm CMOS process. It achieves a batch-calibrated inaccuracy of (3σ) and a trimmed inaccuracy of (3σ) over the temperature range from -70 °C to 125 °C. This performance is obtained by the use of NPN transistors as sensing elements, the use of dynamic techniques, i.e., correlated double sampling and dynamic element matching, and a single room-temperature trim. The sensor draws 8.3 µA from a 1.2-V supply and occupies an area of 0.1 mm².

  @ARTICLE{mine:jssc_2010_temp_sens,
  author = "Fabio Sebastiano and Lucien J. Breems and Kofi Makinwa and Salvatore Drago and Domine M. W. Leenaerts and Bram Nauta",
  journal=IEEE_J_JSSC,
  title="A 1.2-{V} 10-µ{W} {NPN}-Based Temperature Sensor in 65-nm {CMOS} With an Inaccuracy of 0.2 °{C} (3σ) From -70 °{C} to 125 °{C}",
  year={2010},
  month=dec,
  volume={45},
  number={12},
  pages={2591 - 2601},
  abstract={An NPN-based temperature sensor with digital output has been realized in a 65-nm CMOS process. It achieves a batch-calibrated inaccuracy of (3σ) and a trimmed inaccuracy of (3σ) over the temperature range from -70 °C to 125 °C. This performance is obtained by the use of NPN transistors as sensing elements, the use of dynamic techniques, i.e., correlated double sampling and dynamic element matching, and a single room-temperature trim. The sensor draws 8.3 µA from a 1.2-V supply and occupies an area of 0.1 mm².},
  keywords={CMOS integrated circuits;correlation methods;signal sampling;temperature sensors;CMOS;correlated double sampling;dynamic element matching;npn transistor;power 10 muW;size 65 nm;temperature -70 C to 125 C;temperature sensor;voltage 1.2 V;CMOS analog integrated circuits;CMOS process;Intelligent sensors;Sigma delta modulation;Temperature sensors;CMOS analog integrated circuits;sigma-delta modulation;smart sensors;temperature sensors},
  doi={10.1109/JSSC.2010.2076610},
  ISSN={0018-9200}
  }

• F. Sebastiano, L. J. Breems, and R. Roovers, "Automatic Common-mode Rejection Calibration," China patent , patent request 101809863 A , 2010.
  [Bibtex]

  @patent{mine:patent_cmrr_cn,
  author="Fabio Sebastiano and Lucien J. Breems and Raf Roovers",
  title="Automatic Common-mode Rejection Calibration",
  nationality= "China",
  number="101809863 A",
  day="18",
  month=aug,
  year= "2010",
  type="patent request"
  }

• F. Sebastiano, S. Drago, L. J. Breems, and D. M. W. Leenaerts, "Method and system for impulse radio wakeup," Europe patent , patent request 2206240 A2 , 2010.
  [Bibtex]

  @patent{mine:patent_ir2_ep,
  author="Fabio Sebastiano and Salvatore Drago and Lucien J. Breems and Domine M.W. Leenaerts ",
  title="Method and system for impulse radio wakeup",
  nationality= "Europe",
  number="2206240 A2",
  day="14",
  month=jul,
  year= "2010",
  type="patent request"
  }

• F. Sebastiano, S. Drago, L. J. Breems, and D. M. W. Leenaerts, "Method and system for impulse radio wakeup," China patent , patent request 101816130 A , 2010.
  [Bibtex]

  @patent{mine:patent_ir2_cn,
  author="Fabio Sebastiano and Salvatore Drago and Lucien J. Breems and Domine M.W. Leenaerts",
  title="Method and system for impulse radio wakeup",
  nationality= "China",
  number="101816130 A",
  day="25",
  month=aug,
  year= "2010",
  type="patent request"
  }

• S. Drago, F. Sebastiano, D. M. W. Leenaerts, L. J. Breems, and B. Nauta, "Frequency synthesiser," World patent , patent request 113108 A1 , 2010.
  [Bibtex]

  @patent{mine:patent_pll_wo,
  author=" Salvatore Drago and Fabio Sebastiano and Domine M.W. Leenaerts and Lucien J. Breems and Bram Nauta",
  title="Frequency synthesiser",
  nationality= "World",
  number="113108 A1",
  day="7",
  month=oct,
  year= "2010",
  type="patent request"
  }

• S. Drago, F. Sebastiano, D. M. W. Leenaerts, L. J. Breems, and B. Nauta, "Frequency synthesiser," Europe patent , patent request 2237418 A2 , 2010.
  [Bibtex]

  @patent{mine:patent_pll_ep,
  author=" Salvatore Drago and Fabio Sebastiano and Domine M.W. Leenaerts and Lucien J. Breems and Bram Nauta",
  title="Frequency synthesiser",
  nationality= "Europe",
  number="2237418 A2",
  day="6",
  month=oct,
  year= "2010",
  type="patent request"
  }

2009

• S. Drago, D. M. W. Leenaerts, B. Nauta, F. Sebastiano, K. A. A. Makinwa, and L. J. Breems, "A 200 µA duty-cycled PLL for wireless sensor nodes," in Proc. European Solid-State Circuits Conference, Athens, Greece, 2009, pp. 132-135.
  [Abstract] [Bibtex]
  

  A duty-cycled PLL operating in burst mode is presented. It is an essential building block of a moderately accurate low-power frequency synthesizer suitable for use in nodes for wireless sensor networks. Once in lock, the PLL's frequency error is less than 0.1% (rms). Fabricated in a baseline 65 nm CMOS process, the PLL occupies 0.19 times 0.15 mm² and draws 200 µA from a 1.3-V supply when generating a 1 GHz signal with a duty cycle of 10%.

  @INPROCEEDINGS{mine:esscirc_2009_pll,
  author="Salvatore Drago and Domine M.W. Leenaerts and Bram Nauta and Fabio Sebastiano and Kofi A.A. Makinwa and Lucien J. Breems",
  booktitle="Proc. {European Solid-State Circuits Conference}",
  title="A 200 µ{A} duty-cycled {PLL} for wireless sensor nodes",
  year={2009},
  month=sep # {14--18},
  pages={132 - 135},
  address="Athens, Greece",
  abstract={A duty-cycled PLL operating in burst mode is presented. It is an essential building block of a moderately accurate low-power frequency synthesizer suitable for use in nodes for wireless sensor networks. Once in lock, the PLL's frequency error is less than 0.1% (rms). Fabricated in a baseline 65 nm CMOS process, the PLL occupies 0.19 times 0.15 mm² and draws 200 µA from a 1.3-V supply when generating a 1 GHz signal with a duty cycle of 10%.},
  keywords={CMOS integrated circuits;UHF detectors;detector circuits;frequency synthesizers;low-power electronics;phase locked loops;wireless sensor networks;CMOS process;burst mode;current 200 muA;duty cycled PLL;frequency 1 GHz;low power frequency synthesizer;size 0.15 mm;size 0.19 mm;size 65 nm;voltage 1.3 V;wireless sensor nodes;Phase locked loops;Wireless sensor networks},
  doi={10.1109/ESSCIRC.2009.5325979},
  ISSN={1930-8833}
  }

• S. Drago, F. Sebastiano, L. J. Breems, D. M. W. Leenaerts, K. A. A. Makinwa, and B. Nauta, "Impulse-Based Scheme for Crystal-Less ULP Radios," IEEE Trans. Circuits Syst. I, vol. 56, iss. 5, pp. 1041-1052, 2009.
  [Abstract] [Bibtex]
  

  This study describes a method of implementing a fully integrated ultra-low-power (ULP) radio for wireless sensor networks (WSNs). This is achieved using an ad hoc modulation scheme (impulse radio), with a bandwidth of 17.7 MHz in the 2.4 GHz-ISM band and a specific medium access control (MAC) protocol, based on a duty-cycled wake-up radio and a crystal-less clock generator. It is shown that the total average power consumption is expected to be less than 100 µW with a clock generator inaccuracy of only 1%.

  @ARTICLE{mine:tcasi_2009_wsn,
  author={Salvatore Drago and Fabio Sebastiano and Lucien J. Breems and Domine M.W. Leenaerts and Kofi A.A. Makinwa and Bram Nauta},
  journal=IEEE_J_CASI,
  title="Impulse-Based Scheme for Crystal-Less {ULP} Radios",
  year={2009},
  month=may,
  volume={56},
  number={5},
  pages={1041 - 1052},
  abstract={This study describes a method of implementing a fully integrated ultra-low-power (ULP) radio for wireless sensor networks (WSNs). This is achieved using an ad hoc modulation scheme (impulse radio), with a bandwidth of 17.7 MHz in the 2.4 GHz-ISM band and a specific medium access control (MAC) protocol, based on a duty-cycled wake-up radio and a crystal-less clock generator. It is shown that the total average power consumption is expected to be less than 100 µW with a clock generator inaccuracy of only 1%.},
  keywords={access protocols;ad hoc networks;clocks;low-power electronics;modulation;ultra wideband communication;wireless sensor networks;ad hoc modulation;crystal-less ULP radio;crystal-less clock generator;duty-cycled wake-up radio;frequency 17.7 MHz;frequency 2.4 GHz;impulse radio;medium access control protocol;power 100 muW;ultra-low-power radio;wireless sensor network;Crystal-less clock;EDICS Category: COMM110A5, COMM200, COMM250A5;impulse radio;ultra-low power (ULP);wake-up radio;wireless sensor network (WSN)},
  doi={10.1109/TCSI.2009.2015208},
  ISSN={1549-8328}
  }

• F. Sebastiano, L. J. Breems, K. A. A. Makinwa, S. Drago, D. M. W. Leenaerts, and B. Nauta, "A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios," IEEE J. Solid-State Circuits, vol. 44, iss. 7, pp. 2002-2009, 2009.
  [Abstract] [Bibtex]
  

  The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for application in wireless sensor networks (WSN). After a single-point calibration, the spread of its output frequency is less than 1.1% (3σ) over the temperature range from -22 °C to 85 °C . Fabricated in a baseline 65 nm CMOS technology, the frequency reference circuit occupies 0.11 mm² and draws 34 µA from a 1.2 V supply at room temperature.

  @article{mine:jssc_2009_mobility,
  title="A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less {ULP} Radios",
  author="Fabio Sebastiano and Lucien J. Breems and Kofi A.A. Makinwa and Salvatore Drago and Domine M.W. Leenaerts and Bram Nauta",
  journal=IEEE_J_JSSC,
  year={2009},
  month=jul,
  volume={44},
  number={7},
  pages={2002 -2009},
  abstract={The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for application in wireless sensor networks (WSN). After a single-point calibration, the spread of its output frequency is less than 1.1% (3σ) over the temperature range from -22 °C to 85 °C . Fabricated in a baseline 65 nm CMOS technology, the frequency reference circuit occupies 0.11 mm² and draws 34 µA from a 1.2 V supply at room temperature.},
  keywords={CMOS integrated circuits;MOSFET;wireless sensor networks;CMOS technology;MOS transistor;crystal-less ULP radios;current 34 muA;electron mobility;frequency 100 kHz;low-voltage low-power circuit;low-voltage mobility-based frequency reference;size 65 nm;temperature -22 degC to 85 degC;temperature 293 K to 298 K;voltage 1.2 V;wireless sensor networks;CMOS technology;Circuits;Electron mobility;Energy consumption;Frequency synchronization;MOSFETs;Oscillators;Silicon;Temperature sensors;Wireless sensor networks;CMOS analog integrated circuits;Charge carrier mobility;crystal-less clock;low voltage;relaxation oscillators;ultra-low power;wireless sensor networks},
  doi={10.1109/JSSC.2009.2020247},
  ISSN={0018-9200},
  }

• F. Sebastiano, L. J. Breems, and R. Roovers, "Automatic Common-mode Rejection Calibration," World patent , patent request 040697 A3 , 2009.
  [Bibtex]

  @patent{mine:patent_cmrr_wo,
  author="Fabio Sebastiano and Lucien J. Breems and Raf Roovers",
  title="Automatic Common-mode Rejection Calibration",
  nationality= "World",
  number="040697 A3",
  day="6",
  month=aug,
  year= "2009",
  type="patent request"
  }

• S. Drago, F. Sebastiano, D. M. W. Leenaerts, and L. J. Breems, "Power saving method and system for wireless communications device," World patent , patent request 044368 A2 , 2009.
  [Bibtex]

  @patent{mine:patent_ir_wo,
  author="Salvatore Drago and Fabio Sebastiano and Domine M.W. Leenaerts and Lucien J. Breems",
  title="Power saving method and system for wireless communications device",
  nationality= "World",
  number="044368 A2",
  day="9",
  month=apr,
  year= "2009",
  type="patent request"
  }

• F. Sebastiano, S. Drago, L. J. Breems, and D. M. W. Leenaerts, "Method and system for impulse radio wakeup," World patent , patent request 044365 A3 , 2009.
  [Bibtex]

  @patent{mine:patent_ir2_wo,
  author="Fabio Sebastiano and Salvatore Drago and Lucien J. Breems and Domine M.W. Leenaerts ",
  title="Method and system for impulse radio wakeup",
  nationality= "World",
  number="044365 A3",
  day="11",
  month=jun,
  year= "2009",
  type="patent request"
  }

2008

• F. Sebastiano, S. Drago, L. J. Breems, D. M. W. Leenaerts, K. A. A. Makinwa, and B. Nauta, "Impulse Based Scheme for Crystal-less ULP Radios," in Proc. IEEE International Symposium on Circuits and Systems, 2008, pp. 1508-1511.
  [Abstract] [Bibtex]
  

  This study describes a method of implementing a fully integrated ultra-low-power (ULP) radio for wireless sensor networks (WSNs). This is achieved using an ad hoc modulation scheme (impulse radio), with a bandwidth of 17.7 MHz in the 2.4 GHz-ISM band and a specific medium access control (MAC) protocol, based on a duty-cycled wake-up radio and a crystal-less clock generator. It is shown that the total average power consumption is expected to be less than 100 µW with a clock generator inaccuracy of only 1%.

  @inproceedings{mine:iscas_2008_wsn,
  author = "Fabio Sebastiano and Salvatore Drago and Lucien J. Breems and Domine M.W. Leenaerts and Kofi A.A. Makinwa and Bram Nauta",
  month = may # {18--21},
  year = "2008",
  title = "Impulse Based Scheme for Crystal-less {ULP} Radios",
  booktitle = "Proc. {IEEE International Symposium on Circuits and Systems}",
  pages="1508 - 1511",
  abstract={This study describes a method of implementing a fully integrated ultra-low-power (ULP) radio for wireless sensor networks (WSNs). This is achieved using an ad hoc modulation scheme (impulse radio), with a bandwidth of 17.7 MHz in the 2.4 GHz-ISM band and a specific medium access control (MAC) protocol, based on a duty-cycled wake-up radio and a crystal-less clock generator. It is shown that the total average power consumption is expected to be less than 100 µW with a clock generator inaccuracy of only 1%.},
  keywords={access protocols;ad hoc networks;clocks;low-power electronics;modulation;ultra wideband communication;wireless sensor networks;ad hoc modulation;crystal-less ULP radio;crystal-less clock generator;duty-cycled wake-up radio;frequency 17.7 MHz;frequency 2.4 GHz;impulse radio;medium access control protocol;power 100 muW;ultra-low-power radio;wireless sensor network;Crystal-less clock;EDICS Category: COMM110A5, COMM200, COMM250A5;impulse radio;ultra-low power (ULP);wake-up radio;wireless sensor network (WSN)},
  doi={10.1109/TCSI.2009.2015208},
  }

• F. Sebastiano, L. J. Breems, K. A. A. Makinwa, S. Drago, D. M. W. Leenaerts, and B. Nauta, "A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios," in Proc. European Solid-State Circuits Conference, Edinburgh, UK, 2008, pp. 306-309.
  [Abstract] [Bibtex]
  

  The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for Wireless Sensor Networks (WSN) applications. After one-point calibration the spread of its output frequency is less than 1.1% (3σ) over the temperature range from -22 °C to 85 °C. Fabricated in a baseline 65-nm CMOS technology, the frequency reference occupies 0.11 mm² and draws 34 µA from a 1.2-V supply at room temperature.

  @inproceedings{mine:esscirc_2008_mobility,
  title="A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less {ULP} Radios",
  author="Fabio Sebastiano and Lucien J. Breems and Kofi A.A. Makinwa and Salvatore Drago and Domine M.W. Leenaerts and Bram Nauta",
  booktitle="Proc. {European Solid-State Circuits Conference}",
  year="2008",
  pages="306 - 309",
  month=sep # {15--19},
  address="Edinburgh, UK",
  abstract={The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for Wireless Sensor Networks (WSN) applications. After one-point calibration the spread of its output frequency is less than 1.1% (3σ) over the temperature range from -22 °C to 85 °C. Fabricated in a baseline 65-nm CMOS technology, the frequency reference occupies 0.11 mm² and draws 34 µA from a 1.2-V supply at room temperature.},
  keywords={CMOS integrated circuits;MOSFET circuits;electron mobility;integrated circuit design;low-power electronics;mobile radio;wireless sensor networks;MOS transistor;crystal less ULP radios;electron mobility;frequency 100 kHz;low voltage mobility based frequency reference;off-chip components;one point calibration;size 65 nm;temperature -22 degC to 85 degC;voltage 1.2 V;wireless sensor networks;CMOS technology;Calibration;Circuits;Energy consumption;Frequency;Oscillators;Silicon;Temperature distribution;Temperature sensors;Wireless sensor networks},
  doi={10.1109/ESSCIRC.2008.4681853},
  ISSN={1930-8833}
  }

• F. Sebastiano, L. J. Breems, K. A. A. Makinwa, S. Drago, D. M. W. Leenaerts, and B. Nauta, "On the Temperature Compensation of a Frequency Reference for Crystal-Less ULP Wireless Sensor Networks," in Proc. ProRISC, Veldhoven, The Netherlands, 2008, pp. 306-309.
  [Abstract] [Bibtex]
  

  Each node in a Wireless Sensor Network (WSN) must be provided with a frequency reference to enable network synchronization and RF communication. As the nodes need to be small, cheap and energy efcient, a frequency reference suitable for WSN must show low power consumption and require no off-chip components. A reference based on electron mobility in a MOS transistor demonstrates such features. Its output frequency follows the temperature dependence of mobility, which, although large, is well dened and can be compensated for. It is shown that a temperature sensor with accuracy of only 0.6 °C can be employed for the temperature compensation and that the inaccuracy of a compensated mobility-based frequency reference due to temperature, process spread, voltage supply variations and noise can be as low as 1% on a wide temperature range, fitting radio architectures for WSN applications.

  @inproceedings{mine:prorisc_2008_mobility,
  author="Fabio Sebastiano and Lucien J. Breems and Kofi A.A. Makinwa and Salvatore Drago and Domine M.W. Leenaerts and Bram Nauta",
  title="On the Temperature Compensation of a Frequency Reference for Crystal-Less {ULP} Wireless Sensor Networks",
  booktitle="Proc. {ProRISC}",
  year="2008",
  pages="306 - 309",
  month=sep # {27--18},
  address="Veldhoven, The Netherlands",
  abstract={Each node in a Wireless Sensor Network (WSN) must be provided with a frequency reference to enable network synchronization and RF communication. As the nodes need to be small, cheap and energy efcient, a frequency reference suitable for WSN must show low power consumption and require no off-chip components. A reference based on electron mobility in a MOS transistor demonstrates such features. Its output frequency follows the temperature dependence of mobility, which, although large, is well dened and can be compensated for. It is shown that a temperature sensor with accuracy of only 0.6 °C can be employed for the temperature compensation and that the inaccuracy of a compensated mobility-based frequency reference due to temperature, process spread, voltage supply variations and noise can be as low as 1% on a wide temperature range, fitting radio architectures for WSN applications.}
  }

2006

• M. Schipani, F. Sebastiano, N. Nizza, and P. Bruschi, "A fully integrated very low frequency single-ended Gm-C filter based on a novel transconductor," in Proc. IEEE Ph.D. Research in Microelectronics and Electronics, Otranto, Italy, 2006, pp. 25-28.
  [Abstract] [Bibtex]
  

  A second order fully integrated low pass filter with cut-off frequency variable in the range 1.5-15 Hz is presented. The filter is based on a recently proposed CMOS transconductor topology combining G m values of the order of a few nS with large input ranges and suitability to single-ended filter architectures. The performances are validated by simulations performed on a prototype designed with the 0.35 µm BCD6 process of STMicroelectronics. In particular, a dynamic range of 70 dB and power dissipation of 60 µW have been obtained with a corner frequency of 1.5 Hz

  @INPROCEEDINGS{mine:prime_2006_gmc,
  author={Monica Schipani and Fabio Sebastiano and Nicolò Nizza and Paolo Bruschi},
  booktitle="Proc. {IEEE Ph.D. Research in Microelectronics and Electronics}",
  title="A fully integrated very low frequency single-ended {Gm-C} filter based on a novel transconductor",
  year={2006},
  month=jun # {12--15},
  pages={25 - 28},
  address="Otranto, Italy",
  abstract={A second order fully integrated low pass filter with cut-off frequency variable in the range 1.5-15 Hz is presented. The filter is based on a recently proposed CMOS transconductor topology combining G m values of the order of a few nS with large input ranges and suitability to single-ended filter architectures. The performances are validated by simulations performed on a prototype designed with the 0.35 µm BCD6 process of STMicroelectronics. In particular, a dynamic range of 70 dB and power dissipation of 60 µW have been obtained with a corner frequency of 1.5 Hz},
  keywords={CMOS integrated circuits;low-pass filters;network topology;0.35 micron;1.5 to 15 Hz;60 muW;CMOS transconductor topology;low pass filter;second order fully integrated filter;single-ended Gm-C filter;single-ended filter architectures;Capacitance;Capacitors;Frequency;Low pass filters;MOSFETs;Mechanical sensors;Noise reduction;Temperature sensors;Topology;Transconductors},
  doi={10.1109/RME.2006.1689887}
  }

• P. Bruschi, F. Sebastiano, and N. Nizza, "CMOS Transconductors With Nearly Constant Input Ranges Over Wide Tuning Intervals," IEEE Trans. Circuits Syst. II, vol. 53, iss. 10, pp. 1002-1006, 2006.
  [Abstract] [Bibtex]
  

  Three different bias strategies aimed to reduce the effect of tuning on either the differential input range or the common-mode range of triode-region CMOS transconductors are presented. The method is applied to an original transconductor topology that is optimized to produce ultralow Gm values. A prototype circuit, which was designed with the 0.35-µm bipolar-CMOS-DMOS (BCD6) process of STMicroelectronics, is presented. The effectiveness and limitations of the method are characterized by means of electrical simulations

  @ARTICLE{mine:tcasii_2006_tranconductor,
  author={Paolo Bruschi and Fabio Sebastiano and Nicolò Nizza},
  journal=IEEE_J_CASII,
  title="{CMOS} Transconductors With Nearly Constant Input Ranges Over Wide Tuning Intervals",
  year={2006},
  month=oct,
  volume={53},
  number={10},
  pages={1002 - 1006},
  abstract={Three different bias strategies aimed to reduce the effect of tuning on either the differential input range or the common-mode range of triode-region CMOS transconductors are presented. The method is applied to an original transconductor topology that is optimized to produce ultralow Gm values. A prototype circuit, which was designed with the 0.35-µm bipolar-CMOS-DMOS (BCD6) process of STMicroelectronics, is presented. The effectiveness and limitations of the method are characterized by means of electrical simulations},
  keywords={CMOS integrated circuits;bipolar integrated circuits;circuit tuning;0.35 micron;CMOS transconductors;bipolar-CMOS-DMOS process;common-mode range;differential input range;low-frequency filters;prototype circuit;tuning intervals;Chemical sensors;Circuit optimization;Circuit simulation;Low pass filters;MOSFETs;Mirrors;Optimization methods;Stability;Transconductors;Voltage;CMOS transconductor;constant input range;low-frequency filters},
  doi={10.1109/TCSII.2006.882126},
  ISSN={1549-7747}
  }

2005

• P. Bruschi, F. Sebastiano, N. Nizza, and M. Piotto, "A tunable CMOS transconductor for ultra-low Gm with wide differential input voltage range," in Proc. European Conference on Circuit Theory and Design, Cork, Ireland, 2005, p. III/337 - III/340 vol. 3.
  [Abstract] [Bibtex]
  

  A differential input, single ended output transconductor with gm in the range 0.5-5 nS is presented. The circuit uses a source coupled pair operated in triode region. The need of providing a fixed common mode input voltage, which afflicts circuits based on the same principle, is removed by adopting an original topology. The results of simulations based on the 0.35 µm BCD6 process of STMicroelectronics are presented.

  @INPROCEEDINGS{mine:ecctd_2005_gmc,
  author={Paolo Bruschi and Fabio Sebastiano and Nicolò Nizza and Massimo Piotto},
  booktitle="Proc. {European Conference on Circuit Theory and Design}",
  title="A tunable {CMOS} transconductor for ultra-low Gm with wide differential input voltage range",
  year={2005},
  month=aug # {28--} # sep # {2},
  pages={III/337 - III/340 vol. 3},
  address="Cork, Ireland",
  doi={10.1109/ECCTD.2005.1523129},
  abstract={A differential input, single ended output transconductor with gm in the range 0.5-5 nS is presented. The circuit uses a source coupled pair operated in triode region. The need of providing a fixed common mode input voltage, which afflicts circuits based on the same principle, is removed by adopting an original topology. The results of simulations based on the 0.35 µm BCD6 process of STMicroelectronics are presented.}
  }