Cryogenic electronic interfaces for quantum computations

My research on cryo-CMOS interfaces for quantum computing is organized in 4 main themes, as explained in the following.

CryoCMOS modelling

The aim is to characterize devices from several CMOS technologies over a wide range of cryogenic temperatures (30 mK – 77 K) and develop models suitable for analog and digital circuit design over such range. Currently, we have already fabricated and characterized test structures in 0.16-μm CMOS and 40-nm CMOS and, in collaboration with Prof. A. Valdimirescu (UC Berkeley/isep), we have been able to build a device model that is compatible with standard integrated-circuit design tools and that has been used for successfully designing complex analog circuits.

Controllers for quantum processors

Designing a quantum computer will require co-optimizing the classical controller and the quantum processor. We are engineering such system and deriving the specifications for the electronics, by both analyzing and simulating the physics of the quantum devices and by experimenting on existing quantum processors. Today, we are already able to derive a complete set of specifications and trade-offs for the electronic controller for single-electron spin qubits.

CryoCMOS circuits and systems

Capitalizing on my broad research experience on analog/mixed-signal CMOS electronics at room temperature, my group is developing cryogenic circuit blocks to be integrated in the controller, including signal multiplexers and demultiplexers, amplifiers, analog-to-digital and digital-to-analog converters. We will explore the trade-offs between operating temperature, available refrigeration power and functionality, that could result in some components working at 4 K or higher temperatures and others at mK temperatures, possibly on the same die with the qubits. We have already been able to demonstrate the functionality of a low-noise amplifier in a standard CMOS technology operating at 4 K [1, 2].

Cryogenic temperature sensors & references

The objective is the development of supporting electronics for the controller, such as on-chip temperature sensors, references (current, voltage, frequency) and supply regulators, which are required for proper operation of any circuit block at cryogenic temperature. Having characterized the cryogenic behavior of standard CMOS devices employed in integrated voltage references and temperature sensors, we are currently investigating how to use those devices for references and sensors operating over a wide temperature range from 300 K down to 4 K and below.


[1] [doi] E. Charbon, F. Sebastiano, M. Babaie, A. Vladimirescu, M. Shahmohammadi, R. B. Staszewski, H. A. R. Homulle, B. Patra, J. P. G. van Dijk, R. M. Incandela, L. Song, and B. Valizadehpasha, “Cryo-CMOS circuits and systems for scalable quantum computing,” in 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, pp. 264-265.
author={Edoardo Charbon and Fabio Sebastiano and Masoud Babaie and Andrei Vladimirescu and Mina Shahmohammadi and R. B. Staszewski and Harald A. R. Homulle and Bishnu Patra and Jeroen P. G. van Dijk and Rosario M. Incandela and Lin Song and Bahador Valizadehpasha},
booktitle={2017 IEEE International Solid-State Circuits Conference (ISSCC)},
title={Cryo-CMOS circuits and systems for scalable quantum computing},
abstract={In Paper 15.5, Delft University of Technology, EPFL, and Intel present building blocks for a scalable CMOS interface to solid-state quantum processors with a projected efficiency of 200W/qubit. The circuits include an
analog noise-canceled 1.2GHz LNA with 28dB gain, a 6.2GHz class-F local oscillator with better than 145dBc/Hz phase noise at 10MHz offset, a 12µm SPAD with 0.1Hz dark count rate at 2V excess bias, and digital logic, all designed using ad hoc deep-cryogenic models.},
keywords={CMOS integrated circuits;logic circuits;quantum computing;cryo-CMOS circuits;error-correcting loop;quantum algorithm;quantum bits arrays;quantum coherence loss;qubit states;room-temperature controller;scalable quantum computing;state-of-the-art quantum processors;unprecedented computation power;Cryogenics;Oscillators;Program processors;Quantum computing;Semiconductor
device modeling;Substrates;Temperature sensors},
[2] [doi] B. Patra, R. M. Incandela, J. P. G. van Dijk, H. A. R. Homulle, L. Song, M. Shahmohammadi, R. B. Staszewski, A. Vladimirescu, M. Babaie, F. Sebastiano, and E. Charbon, “Cryo-CMOS Circuits and Systems for Quantum Computing Applications,” IEEE Journal of Solid-State Circuits, vol. 53, iss. 1, pp. 1-13, 2018.
author={Bishnu Patra and Rosario M. Incandela and Jeroen P. G. van Dijk and Harald A. R. Homulle and Lin Song and Mina Shahmohammadi and Robert B. Staszewski and Andrei Vladimirescu and Masoud Babaie and Fabio Sebastiano and Edoardo Charbon},
journal={IEEE Journal of Solid-State Circuits},
title={Cryo-CMOS Circuits and Systems for Quantum Computing Applications},
abstract={A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum computers. In this paper, a cryogenic control system is proposed, along with the required specifications, for the interface of the classical electronics with the quantum processor. To prove the advantages of such a system, the functionality of key circuit blocks is experimentally demonstrated. The characteristic properties of cryo-CMOS are exploited to design a noise-canceling low-noise amplifier for spin-qubit RF-reflectometry readout and a class-F2,3 digitally controlled oscillator required to manipulate the state of qubits.},
keywords={CMOS technology;Cryogenics;Oscillators;Process control;Quantum computing;Temperature;CMOS characterization;Class-F oscillator;cryo-CMOS;low-noise amplifier (LNA);noise canceling;phase noise (PN);quantum bit (qubit);quantum computing;qubit control;single-photon avalanche diode (SPAD).},